CAD for Assurance of Electronic Systems

Reverse Engineering Attacks


Massive outsourcing of the integrated circuit (IC) design and manufacturing processes (fabless model), as well as increased demand for commercial and custom ICs in the government and the commercial sectors, have raised reliability and security issues. Aiding to the cause is the increasing complexity of IC designs and shorter Time-To-Market (TTM), which has led to the insertion of intentional (hardware Trojan, backdoors) and unintentional flaws at various levels of the IC production process. Techniques for the detection of such flaws require reverse engineering (RE) of ICs, which involves identifying the device technology used in it, extracting its gate-level netlist, and/or inferring its functionality. Tools and techniques that have been developed for RE of ICs can be misused by an attacker to steal the design, identify the device technology for competitive advantage, or illegally fabricate the target IC. To achieve these objectives, an attacker will attempt to RE the design to the target level of abstraction, which can vary depending on the objective of the attacker. If the objective is to steal the design, then the target abstraction level can be either the physical design level, the gate-level, or the RT level, whereas if the goal is to insert malicious logic then the target abstraction level can be either the gate-level or the RT level. In the semiconductor supply chain, an RE attacker can be present in either the design integration house, the foundry, or it can be the user. To prevent such an attack, tools such as Network Flow Attack For Split Manufacturing, ObfusGEM, NETA, and Deep Learning Based Model Building Attacks on Arbiter PUF Compositions have been developed.

Related Tools


Zuzak, Michael; Srivastava, Ankur

ObfusGEM: Enhancing Processor Design Obfuscation Through Security-Aware On-Chip Memory and Data Path Design Proceedings Article

In: International Symposium on Memory Systems (MEMSYS), 2020.


Portillo, Jason; Meade, Travis; Hacker, John; Zhang, Shaojie; Jin, Yier

RERTL: Finite State Transducer Logic Recovery at Register Transfer Level Proceedings Article

In: 2019 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), pp. 1-6, ASIAN-HOST IEEE, Xi'an, P.R. China, 2019.

Abstract | Links | BibTeX

Meade, Travis; Portillo, Jason; Zhang, Shaojie; Jin, Yier

NETA: When IP Fails, Secrets Leak Proceedings Article

In: Proceedings of the 24th Asia and South Pacific Design Automation Conference, pp. 90–95, Association for Computing Machinery, Tokyo, Japan, 2019, ISBN: 9781450360074.

Abstract | Links | BibTeX

Facon, Adrien; Guilley, Sylvain; Lec'hvien, Matthieu; Marion, Damien; Perianin, Thomas

Binary Data Analysis for Source Code Leakage Assessment Proceedings Article

In: Innovative Security Solutions for Information Technology and Communications, pp. 391–409, Springer International Publishing, Cham, 2019, ISBN: 978-3-030-12942-2.

Abstract | Links | BibTeX

Souissi, Youssef; Facon, Adrien; Guilley, Sylvain

Virtual Security Evaluation Proceedings Article

In: Carlet, Claude; Guilley, Sylvain; Nitaj, Abderrahmane; Souidi, El Mamoun (Ed.): Codes, Cryptology and Information Security, pp. 3–12, Springer International Publishing, Cham, 2019, ISBN: 978-3-030-16458-4.

Abstract | Links | BibTeX

Meade, Travis; Shamsi, Kaveh; Le, Thao; Di, Jia; Zhang, Shaojie; Jin, Yier

The Old Frontier of Reverse Engineering: Netlist Partitioning Journal Article

In: Journal of Hardware and Systems Security, vol. 2, no. 3, pp. 201-213, 2018.

Abstract | Links | BibTeX

Mathieu, Brandon L.; McCue, Jamin J.; Duncan, Lucas; Dupaix, Brian; Lavasani, Hossein Miri; Khalil, Waleed

A Capacitively Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver Journal Article

In: IEEE Journal of Solid-State Circuits, vol. 53, no. 9, pp. 2500-2511, 2018, ISSN: 1558-173X.

Abstract | Links | BibTeX

Takarabt, Sofiane; Chibani, Kais; Facon, Adrien; Guilley, Sylvain; Mathieu, Yves; Sauvage, Laurent; Souissi, Youssef

Pre-silicon Embedded System Evaluation as New EDA Tool for Security Verification Proceedings Article

In: 2018 IEEE 3rd International Verification and Security Workshop (IVSW), pp. 74-79, 2018.

Abstract | Links | BibTeX

Wang, Yujie; Chen, Pu; Hu, Jiang; Li, Guofeng; Rajendran, Jeyavijayan

The Cat and Mouse in Split Manufacturing Journal Article

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 5, pp. 805-817, 2018, ISSN: 1557-9999.

Abstract | Links | BibTeX

Meade, Travis; Zhao, Zheng; Zhang, Shaojie; Pan, David Z.; Jin, Yier

Revisit Sequential Logic Obfuscation: Attacks and Defenses Proceedings Article

In: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, IEEE, Baltimore, MD, USA , 2017.

Abstract | Links | BibTeX

Meade, Travis; Jin, Yier; Tehranipoor, Mark; Zhang, Shaojie

Gate-Level Netlist Reverse Engineering for Hardware Security: Control Logic Register Identification Proceedings Article

In: 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1334-1337, IEEE, Montreal, QC, Canada, 2016.

Abstract | Links | BibTeX

Meade, Travis; Zhang, Shaojie; Jin, Yier

Netlist Reverse Engineering for High-Level Functionality Reconstruction Proceedings Article

In: 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 655-660, ASP-DAC IEEE, Macau, 2016, (Best Paper Award).

Abstract | Links | BibTeX