CAD for Assurance of Electronic Systems

NETA: Netlist Analysis Toolset

By: Travis Meade, Shaojie Zhang, and Yier Jin

Stage: Gate level


  • NETA is a comprehensive framework for gate-level netlist security analysis, which takes gate-level netlist as the input and recover the RTL description for security evaluation.
  • The tools in NETA include:
    • RELIC2 for netlist partitioning and logic identification.
    • REFSM for function recovery.
    • REPATH for function recovery.
    • REBUS: for data flow analysis.
    • REPCA: for words matching.
    • Tarjan’s Strongly Connected Component (SCC) Algorithm for function behavior detection.
    • REDPEN for register interaction analysis.


  • RELIC2: ./logic_identification/bin/relic --net <netlist_file_name>
  • REFSM: ./logic_extraction/bin/refsm --net <netlist_file_name> --lib data/libraries/typical_xor.rib --word <uart_word_file_name> --csv uart > <output_file_name>
  • REPATH: ./logic_extraction/bin/repath --net <netlist_file_name> --word <word_file_name> --bs <base_state_file_name>
  • REBUS: ./word_partition/bin/rebus --net <netlist_file_name> --lib data/libraries/typical_xor.rib --word <word_file_name>
  • REPCA: ./word_partition/bin/repca --net <netlist_file_name> --lib data/libraries/typical_xor.rib --feat <feat_file_name> --out <output_file_name> --persplt .01
  • Tarjan’s SCC Algorithm: ./misc_tools/bin/tjscc --tran <sransition_file_name>
  • REDPEN: ./misc_tools/bin/tjscc --net <netlist_file_name>


Yier Jin

Licensing Info

The tools are free for non-commercial usage. Please use at your own discretion. For commercial use, please contact Dr. Yier Jin.

(C) 2018 Travis Meade, Shaojie Zhang, Yier Jin

Toolset can be found at:


Meade, Travis; Portillo, Jason; Zhang, Shaojie; Jin, Yier

NETA: When IP Fails, Secrets Leak Proceedings Article

In: Proceedings of the 24th Asia and South Pacific Design Automation Conference, pp. 90–95, Association for Computing Machinery, Tokyo, Japan, 2019, ISBN: 9781450360074.

Abstract | Links | BibTeX

Meade, Travis; Shamsi, Kaveh; Le, Thao; Di, Jia; Zhang, Shaojie; Jin, Yier

The Old Frontier of Reverse Engineering: Netlist Partitioning Journal Article

In: Journal of Hardware and Systems Security, vol. 2, no. 3, pp. 201-213, 2018.

Abstract | Links | BibTeX

Meade, Travis; Zhao, Zheng; Zhang, Shaojie; Pan, David Z.; Jin, Yier

Revisit Sequential Logic Obfuscation: Attacks and Defenses Proceedings Article

In: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, IEEE, Baltimore, MD, USA , 2017.

Abstract | Links | BibTeX

Meade, Travis; Jin, Yier; Tehranipoor, Mark; Zhang, Shaojie

Gate-Level Netlist Reverse Engineering for Hardware Security: Control Logic Register Identification Proceedings Article

In: 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1334-1337, IEEE, Montreal, QC, Canada, 2016.

Abstract | Links | BibTeX

Meade, Travis; Zhang, Shaojie; Jin, Yier

Netlist Reverse Engineering for High-Level Functionality Reconstruction Proceedings Article

In: 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 655-660, ASP-DAC IEEE, Macau, 2016, (Best Paper Award).

Abstract | Links | BibTeX


  • The work is partially supported by the National Science Foundation (NSF-1812071, NSF-1703602)