CAD for Assurance of Electronic Systems

DIFTV: Dynamic Information Flow Tracking on RISC-V

By: Kejun Chen, Yier Jin

Stage: RTL


  • A framework to detect the software attacks at run-time.
  • Implemented as a coprocessor which attached to the RISC-V processor core Rocket-Chip.
  • The committed instructions will be sent to the coprocessor for further analyzing.
  • The security check policy is customized based on the custom RISC-V instructions.
  • The related information flow will be check according to the customized security policy.


Yier Jin


  • The work is partially supported by the National Science Foundation (NSF / CNS, 1801599, NSF / CCF, 2019283)