By: A V Lakshmy (IIT Madras), Chester Rebeiro (IIT Madras), and Swarup Bhunia (University of Florida)
Stage: RTL, HDL, Gate-Level
Summary
- FORTIFY is an analytical framework that can efficiently estimate the fine-grained power side-channel leakage of hardware designs, early on in the design cycle (at the RTL or gate-level netlist stage).
- FORTIFY quantifies the information leakage at each gate in the design by representing the design as a directed graph, performing static information flow analysis on this graph to identify the portions of the design that are influenced by a security asset (or reference signal) in the design, and applying a mathematical model based on signal probabilities to estimate the leakage scores for each signal in the design (with respect to this reference signal).
- FORTIFY’s analytical approach makes it at least 100 times faster than contemporary pre-Silicon power side-channel vulnerability estimation techniques based on statistical analysis, which require a large number of time-consuming simulations.
Contact
Input/Output Interface
- Input: Hardware design provided in RTL / Gate-level netlist (Verilog); A reference signal in the design
- Output: A list of leakage scores for each signal in the design
Dependencies
Python 3, certain Python modules (tqdm, pyverilog, z3-solver, numpy, scipy, Verilog_VCD, pandas, matplotlib)
Licensing Info
BSD 3-Clause License Copyright (c) 2012-2020, IIT-Madras All rights reserved.
References
FORTIFY: Analytical Pre-Silicon Side-Channel Leakage Characterization of Digital Designs Proceedings Article Forthcoming
In: ASP-DAC, Forthcoming.
Acknowledgments
- We thank the Qualcomm Innovation Fellowship 2020-21 and the Samsung-IITM Pravartak Fellowship for their support.
User Guide Link can be found at this link
Additional Information
- FORTIFY does not support analysis of sequential designs, which have cyclic dependencies.