CAD for Assurance of Electronic Systems

KHC-Stego Tool: Key-Triggered Hash-Chaining Driven Steganography Tool

By: Anirban Sengupta (IIT Indore) and Mahendra Rathor (IIT Indore)

Stage: RTL


Summary and Threat Model: KHC-Stego tool simulates and analyses the functionality of key-triggered hash-chaining driven steganography approach for securing DSP hardware accelerators against piracy and false claim of ownership threats.

Objective of the tool: The left portion of the tool shows the panel for providing required inputs to the tool, right portion shows the panel with output buttons to see the intermediate and final outputs of the key-triggered hash-chaining based steganography approach. The panel in the middle shows the status of the intermediate steps viz. CDFG scheduling of DSP application, encoding selection, executing hash-chaining process and insert constraints. Initially, these status bars remain red. Upon applying the inputs, the respective status bar turns green. The KHC-Stego tool accepts the DSP application input in the form CDFG along with module library and resource constraints. The tool shows output of intermediate steps of key-triggered hash-chaining based steganography, finally generated stego-constraints, the security metric in terms of probability of coincidence, pre and post-steganography design cost. Further, it also shows scheduling and registers allocation pre and post-embedding steganography constraints, onto the output window. The embedded steganography constraints in the hardware accelerator design can be used as digital evidence to secure against piracy and false claim of ownership threats.


Dr. Anirban Sengupta and Mahendra Rathor

Input/Output Interface

  • Input:
    • Text file of DFG representation of DSP application
    • module library
    • resource constraints (i.e. # adders, multipliers etc.)
    • number of encodings
    • chosen order of encodings
    • stego-key
    • # rounds of hashes
    • constraints size
  • Output:
    • Scheduled DFG pre-steganography
    • register allocation table pre-steganography
    • design cost pre-steganography (i.e. baseline cost)
    • scheduled DFG post-steganography
    • register allocation table post-steganography
    • design cost post-steganography phase-1
    • design cost post-steganography phase-2 (final cost)
    • Pc post-steganography phase-1
    • post-steganography phase-2 (final Pc)


OS: Windows 10


Sengupta, Anirban

Key-triggered Hash-chaining based Encoded Hardware Steganography for Securing DSP Hardware Accelerators Book Forthcoming

Forthcoming, ISBN: 978-1-83953-306-8.


Rathor, Mahendra; Sengupta, Anirban

IP Core Steganography Using Switch Based Key-Driven Hash-Chaining and Encoding for Securing DSP Kernels Used in CE Systems Journal Article

In: IEEE Transactions on Consumer Electronics, vol. 66, no. 3, pp. 251-260, 2020, ISSN: 1558-4127.

Abstract | Links | BibTeX


  • Indian Institute of Technology Indore; Ministry of Electronics & Information Technology (MEitY) Govt. of India; Council of Industrial & Scientific Research (CSIR) -EMR Division