CAD for Assurance of Electronic Systems

QFlow: Quantifying Data Leakage for RTL IP

By: Lennart Reimann (RWTH Aachen University), Luca Hanel (RWTH Aachen University), Dominik Sisejkovic (RWTH Aachen University), Farhad Merchant (RWTH Aachen University), and Rainer Leupers (RWTH Aachen University)

Stage: RTL


  • A tool that detects hardware vulnerabilities of a hardware description at register transfer level
  • Developers need to mark sensitive signals that are supposed to be kept secret
  • QFlow quantifies data leakages caused by accidental design mistakes or hardware Trojans to untrusted hardware components
  • Developers will receive the leakages paths in the hardware and a leakage value (in bit) for every single secret bit
  • Quantitative Information Flow is used for the computations in the tool


Lennart Reimann

Input/Output Interface

  • Input: Denoted Verilog Program, probability distributions of the inputs
  • Output: Leakage paths, leakage values



Licensing Info

For now: the tool is not yet available online


Reimann, Lennart M.; Hanel, Luca; Sisejkovic, Dominik; Merchant, Farhad; Leupers, Rainer

QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog Proceedings Article

In: IEEE International Conference on Computer Design, 2021.

Abstract | Links | BibTeX