Obfuscated Benchmarks: Sequential Obfuscation (ProtectIP)

@article{5247148,

title = {HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection},

author = {Rajat Subhra Chakraborty and Swarup Bhunia},

doi = {10.1109/TCAD.2009.2028166},

issn = {1937-4151},

year  = {2009},

date = {2009-10-01},

journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},

volume = {28},

number = {10},

pages = {1493-1502},

abstract = {Hardware intellectual-property (IP) cores have emerged as an integral part of modern system-on-chip (SoC) designs. However, IP vendors are facing major challenges to protect hardware IPs from IP piracy. This paper proposes a novel design methodology for hardware IP protection using netlist-level obfuscation. The proposed methodology can be integrated in the SoC design and manufacturing flow to simultaneously obfuscate and authenticate the design. Simulation results for a set of ISCAS-89 benchmark circuits and the advanced-encryption-standard IP core show that high levels of security can be achieved at less than 5% area and power overhead under delay constraint.},

keywords = {},

pubstate = {published},

tppubtype = {article}

}