By: Xiaolong Guo and Yier Jin
- A framework which evaluates the trustworthiness of a hardware system at register transfer level (RTL).
- Includes a quantified information flow (QIF) model and extends Verilog/VHDL type systems
- Help developers with no security background to label sensitive signals and to quickly evaluate the design’s trustworthiness levels.
- Initial results for 18 benchmarks using leakage paths as design errors show detection accuracy of 100% without false positive in less than 20 minutes.
- Input: Denoted Verilog program
- Output: Whether there is information leakage vulnerability
- Icarus Verilog
Instruction: Run on linux command: ./qif –help
In: 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 91-100, IEEE, McLean, VA, USA, 2019.
- This work is partially supported by Army Research Office (W911NF-17-1-0477), Semiconductor Research Corporation (2014-TS-2