CAD for Assurance of Electronic Systems

SIGNED: Secure Lightweight Watermarking Framework

By: Abhishek Nair (IIT Madras), Patanjali SLPSK (University of Florida), Chester Rebeiro (IIT Madras), Swarup Bhunia (University of Florida)

Stage: Gate-Level


SIGNED is a fully automated commercial quality tool that inserts a watermark in hard-ware intellectual property (IP). The tool first partitions the design, then selects a set of representative nets and challenge vectors. When the challenge vectors are applied to the primary inputs of the design, the Boolean values of the representative nets will contain structural information regarding the design. SIGNED also introduces a compactor function into the design which compresses the Boolean values of the representative nets into a design response (Primary Outputs). If a malicious entity structurally tampers with the design, the Boolean values of the representative nets will have different values than the Boolean values in the original untampered design. Therefore, the tampering can be detected by comparing the design response of the tampered design with the design response of the untampered design.


Input/Output Interface

  • Input: Flattened gate-level netlist, Standard library cell
  • Output: Hardware Watermarked design; Debugging Info



Licensing Info

The tool is available for licensing through University of Florida licensing office. The underlying technology is under patent pending. Please contact for licensing options. Please refer to the tool as FOWL in such communications


Nair, Abhishek; SLPSK, Patanjali; Rebeiro, Chester; Bhunia, Swarup

SIGNED: A Challenge-Response Based Interrogation Scheme for Simultaneous Watermarking and Trojan Detection Miscellaneous


Links | BibTeX


  • University of Florida; Indian Institute of Technology Madras