CAD for Assurance of Electronic Systems

RTL Locking+Watermarking

By: Yier Jin

Stage: RTL


  • An FSM-based IP watermarking generation and integration method to generate a watermark-embedded FSM in RTL code.


Yier Jin


  • Configuration setup: configuration_file.txt
  • Watermarking generation: create_FSM_12
    • Input: FSM-input.txt
    • Output: HDL_code.v, testbench.v, signature_information.txt
  • Simulation: any simulation tool can be used to simulate the generated HDL_code.v file
    • Input: HDL_code.v
    • Output: FSM-output_test.txt
  • Watermark validation: recover_information
    • Input: FSM-output_test.txt, signature_information.txt
    • Output: whether the extract watermark is correct
  • Download link:


  • PyCryptodome