@article{Babecki2016Embedded,
title = {An Embedded Memory-Centric Reconfigurable Hardware Accelerator for Security Applications},
author = {Christopher Babecki and Wenchao Qian and Somnath Paul and Robert Karam and Swarup Bhunia},
doi = {10.1109/TC.2015.2512858},
issn = {1557-9956},
year = {2016},
date = {2016-10-01},
journal = {IEEE Transactions on Computers},
volume = {65},
number = {10},
pages = {3196-3202},
abstract = {Security has emerged as a critical need in today's computer applications. Unfortunately, most security algorithms are computationally expensive and often do not map efficiently to general purpose processors. Fixed-function accelerators offer significant improvement in energy-efficiency, but they do not allow more than one application to reuse hardware resources. Mapping applications to generic reconfigurable fabrics can achieve the desired flexibility, but at the cost of area and energy efficiency. This paper presents a novel reconfigurable framework, referred to as hardware accelerator for security kernel (HASK), for accelerating a wide array of security applications. This framework incorporates a coarse-grained datapath, supports for lookup functions, and flexible interconnect optimizations, which enable on-demand pipelining and parallel computations in multiple ultralight-weight processing elements. These features are highly effective for energy-efficient operation in a diverse set of security applications. Through simulations, we have compared the performance of HASK to software and field programmable gate array (FPGA) platforms. Simulation results for a set of six common security applications show comparable latency between HASK and FPGA with 2.5X improvement in energy-delay product and 4X improvement in iso-area throughput. HASK also shows 5X improvement in iso-area throughput and 45X improvement in energy-delay product compared to optimized software implementations.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}