By: Embedded Security Group, Max Planck Institute for Security and Privacy, Germany
HAL [/hel/] is a comprehensive netlist reverse engineering and manipulation framework.
Virtually all available research on netlist analysis operates on a graph-based representation of the netlist under inspection. At its core, HAL provides exactly that: A framework to parse netlists of arbitrary sources, e.g., FPGAs or ASICs, into a graph-based netlist representation and to provide the necessary built-in tools for traversal and analysis of the included gates and nets.
Our vision is that HAL becomes the hardware-reverse-engineering-equivalent of tools like IDA or Ghidra. We want HAL to enable a common baseline for researchers and analysts to improve reproducibility of research results and abstract away recurring basic tasks such as netlist parsing etc.
- Input: A netlist to analyze
- Output: Whatever your analysis plugins can provide
Since HAL is under active development dependencies can change over time.
Please check our git repo to find the most recent information.
In: IEEE Transactions on Dependable and Secure Computing, vol. 16, no. 3, pp. 498-510, 2019, ISSN: 1941-0018.
In: Proceedings of the 16th ACM International Conference on Computing Frontiers, pp. 392–397, Association for Computing Machinery, Alghero, Italy, 2019, ISBN: 9781450366854.
- This work was partially supported by ERC Advanced Grant No. 695022