2021
Faezi, Sina; Yasaei, Rozhin; Barua, Anomadarshi; Faruque, Mohammad Abdullah Al
Brain-Inspired Golden Chip Free Hardware Trojan Detection Journal Article
In: IEEE Transactions on Information Forensics and Security, vol. 16, pp. 2697–2708, 2021.
Abstract | Links | BibTeX | Tags: Side Channel Analysis
@article{Faezi2021Brain,
title = {Brain-Inspired Golden Chip Free Hardware Trojan Detection},
author = {Sina Faezi and Rozhin Yasaei and Anomadarshi Barua and Mohammad Abdullah Al Faruque},
url = {https://doi.org/10.1109/tifs.2021.3062989},
doi = {10.1109/tifs.2021.3062989},
year = {2021},
date = {2021-01-01},
journal = {IEEE Transactions on Information Forensics and Security},
volume = {16},
pages = {2697--2708},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
abstract = {Since 2007, the use of side-channel measurements for detecting Hardware Trojan (HT) has been extensively studied. However, the majority of works either rely on a golden chip, or they rely on methods that are not robust against subtle acceptable changes that would occur over the life-cycle of an integrated circuit (IC). In this paper, we propose using a brain-inspired architecture called Hierarchical Temporal Memory (HTM) for HT detection. Similar to the human brain, our proposed solution is resilient against <italic>natural</italic> changes that might happen in the side-channel measurements while being able to accurately detect abnormal behavior of the chip when the HT gets triggered. We use a self-referencing method for HT detection, which eliminates the need for the golden chip. The effectiveness of our approach is evaluated using TrustHub benchmarks, which shows 92.20% detection accuracy on average.},
keywords = {Side Channel Analysis},
pubstate = {published},
tppubtype = {article}
}
Since 2007, the use of side-channel measurements for detecting Hardware Trojan (HT) has been extensively studied. However, the majority of works either rely on a golden chip, or they rely on methods that are not robust against subtle acceptable changes that would occur over the life-cycle of an integrated circuit (IC). In this paper, we propose using a brain-inspired architecture called Hierarchical Temporal Memory (HTM) for HT detection. Similar to the human brain, our proposed solution is resilient against <italic>natural</italic> changes that might happen in the side-channel measurements while being able to accurately detect abnormal behavior of the chip when the HT gets triggered. We use a self-referencing method for HT detection, which eliminates the need for the golden chip. The effectiveness of our approach is evaluated using TrustHub benchmarks, which shows 92.20% detection accuracy on average.
2020
F, Muhammad Arsath K; Ganesan, Vinod; Bodduna, Rahul; Rebeiro, Chester
PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance Proceedings Article
In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 23-34, 2020.
Abstract | Links | BibTeX | Tags: Side Channel Analysis
@inproceedings{KPARAM2020,
title = {PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance},
author = {Muhammad Arsath K F and Vinod Ganesan and Rahul Bodduna and Chester Rebeiro},
doi = {10.1109/HOST45689.2020.9300263},
year = {2020},
date = {2020-12-01},
booktitle = {2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)},
pages = {23-34},
abstract = {The power consumption of a microprocessor is a huge channel for information leakage. While the most popular exploitation of this channel is to recover cryptographic keys from embedded devices, other applications such as mobile app fingerprinting, reverse engineering of firmware, and password recovery are growing threats. Countermeasures proposed so far are tuned to specific applications, such as crypto-implementations. They are not scalable to the large number and variety of applications that typically run on a general purpose microprocessor.In this paper, we investigate the design of a microprocessor, called PARAM with increased resistance to power based sidechannel attacks. To design PARAM, we start with identifying the most leaking modules in an open-source RISC V processor. We evaluate the leakage in these modules and then add suitable countermeasures. The countermeasures depend on the cause of leakage in each module and can vary from simple modifications of the HDL code ensuring secure translation by the EDA tools, to obfuscating data and address lines thus breaking correlation with the processor's power consumption. The resultant processor is instantiated on the SASEBO-GIII FPGA board and found to resist Differential Power Analysis even after one million power traces. Compared to contemporary countermeasures for power side-channel attacks, overheads in area and frequency are minimal.},
keywords = {Side Channel Analysis},
pubstate = {published},
tppubtype = {inproceedings}
}
The power consumption of a microprocessor is a huge channel for information leakage. While the most popular exploitation of this channel is to recover cryptographic keys from embedded devices, other applications such as mobile app fingerprinting, reverse engineering of firmware, and password recovery are growing threats. Countermeasures proposed so far are tuned to specific applications, such as crypto-implementations. They are not scalable to the large number and variety of applications that typically run on a general purpose microprocessor.In this paper, we investigate the design of a microprocessor, called PARAM with increased resistance to power based sidechannel attacks. To design PARAM, we start with identifying the most leaking modules in an open-source RISC V processor. We evaluate the leakage in these modules and then add suitable countermeasures. The countermeasures depend on the cause of leakage in each module and can vary from simple modifications of the HDL code ensuring secure translation by the EDA tools, to obfuscating data and address lines thus breaking correlation with the processor's power consumption. The resultant processor is instantiated on the SASEBO-GIII FPGA board and found to resist Differential Power Analysis even after one million power traces. Compared to contemporary countermeasures for power side-channel attacks, overheads in area and frequency are minimal.
F, Muhammad Arsath K; Ganesan, Vinod; Bodduna, Rahul; Rebeiro, Chester
PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance Journal Article
In: 2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2020.
Links | BibTeX | Tags: SCA Attacks, Side Channel Analysis
@article{arsath2020param,
title = {PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance},
author = {Muhammad Arsath K F and Vinod Ganesan and Rahul Bodduna and Chester Rebeiro},
url = {http://dx.doi.org/10.1109/HOST45689.2020.9300263},
doi = {10.1109/host45689.2020.9300263},
year = {2020},
date = {2020-12-01},
journal = {2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)},
publisher = {IEEE},
keywords = {SCA Attacks, Side Channel Analysis},
pubstate = {published},
tppubtype = {article}
}
0000
Lakshmy, A V; Rebeiro, Chester; Bhunia, Swarup
FORTIFY: Analytical Pre-Silicon Side-Channel Leakage Characterization of Digital Designs Proceedings Article Forthcoming
In: ASP-DAC, Forthcoming.
BibTeX | Tags: Side Channel Analysis
@inproceedings{nokey,
title = {FORTIFY: Analytical Pre-Silicon Side-Channel Leakage Characterization of Digital Designs},
author = {A V Lakshmy and Chester Rebeiro and Swarup Bhunia},
booktitle = {ASP-DAC},
keywords = {Side Channel Analysis},
pubstate = {forthcoming},
tppubtype = {inproceedings}
}