2020
Nair, Abhishek; SLPSK, Patanjali; Rebeiro, Chester; Bhunia, Swarup
SIGNED: A Challenge-Response Based Interrogation Scheme for Simultaneous Watermarking and Trojan Detection Miscellaneous
2020.
Links | BibTeX | Tags: IC Trust Verification
@misc{nair2020signed,
title = {SIGNED: A Challenge-Response Based Interrogation Scheme for Simultaneous Watermarking and Trojan Detection},
author = {Abhishek Nair and Patanjali SLPSK and Chester Rebeiro and Swarup Bhunia},
url = {https://arxiv.org/abs/2010.05209},
year = {2020},
date = {2020-01-01},
keywords = {IC Trust Verification},
pubstate = {published},
tppubtype = {misc}
}
2016
Huang, Yuanwen; Bhunia, Swarup; Mishra, Prabhat
MERS: Statistical Test Generation for Side-Channel Analysis Based Trojan Detection Proceedings Article
In: Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security, pp. 130–141, Association for Computing Machinery, Vienna, Austria, 2016, ISBN: 9781450341394.
Abstract | Links | BibTeX | Tags: IC Trust Verification
@inproceedings{10.1145/2976749.2978396,
title = {MERS: Statistical Test Generation for Side-Channel Analysis Based Trojan Detection},
author = {Yuanwen Huang and Swarup Bhunia and Prabhat Mishra},
url = {https://doi.org/10.1145/2976749.2978396},
doi = {10.1145/2976749.2978396},
isbn = {9781450341394},
year = {2016},
date = {2016-01-01},
booktitle = {Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security},
pages = {130–141},
publisher = {Association for Computing Machinery},
address = {Vienna, Austria},
series = {CCS ’16},
abstract = {Hardware Trojan detection has emerged as a critical challenge to ensure security and trustworthiness of integrated circuits. A vast majority of research efforts in this area has utilized side-channel analysis for Trojan detection. Functional test generation for logic testing is a promising alternative but it may not be helpful if a Trojan cannot be fully activated or the Trojan effect cannot be propagated to the observable outputs. Side-channel analysis, on the other hand, can achieve significantly higher detection coverage for Trojans of all types/sizes, since it does not require activation/propagation of an unknown Trojan. However, they have often limited effectiveness due to poor detection sensitivity under large process variations and small Trojan footprint in side-channel signature. In this paper, we address this critical problem through a novel side-channel-aware test generation approach, based on a concept of Multiple Excitation of Rare Switching (MERS), that can significantly increase Trojan detection sensitivity. The paper makes several important contributions: i) it presents in detail the statistical test generation method, which can generate high-quality testset for creating high relative activity in arbitrary Trojan instances; ii) it analyzes the effectiveness of generated testset in terms of Trojan coverage; and iii) it describes two judicious reordering methods can further tune the testset and greatly improve the side channel sensitivity. Simulation results demonstrate that the tests generated by MERS can significantly increase the Trojans sensitivity, thereby making Trojan detection effective using side-channel analysis.},
keywords = {IC Trust Verification},
pubstate = {published},
tppubtype = {inproceedings}
}
2009
Chakraborty, Rajat Subhra; Wolff, Francis; Paul, Somnath; Papachristou, Christos; Bhunia, Swarup
MERO: A Statistical Approach for Hardware Trojan Detection Proceedings Article
In: Clavier, Christophe; Gaj, Kris (Ed.): Cryptographic Hardware and Embedded Systems - CHES 2009, pp. 396-410, Springer Berlin Heidelberg, Berlin, Heidelberg, 2009, ISBN: 978-3-642-04138-9.
Abstract | Links | BibTeX | Tags: IC Trust Verification
@inproceedings{10.1007/978-3-642-04138-9_28,
title = {MERO: A Statistical Approach for Hardware Trojan Detection},
author = {Rajat Subhra Chakraborty and Francis Wolff and Somnath Paul and Christos Papachristou and Swarup Bhunia},
editor = {Christophe Clavier and Kris Gaj},
url = {https://doi.org/10.1007/978-3-642-04138-9_28},
doi = {10.1007/978-3-642-04138-9_28},
isbn = {978-3-642-04138-9},
year = {2009},
date = {2009-01-01},
booktitle = {Cryptographic Hardware and Embedded Systems - CHES 2009},
pages = {396-410},
publisher = {Springer Berlin Heidelberg},
address = {Berlin, Heidelberg},
abstract = {In order to ensure trusted in-field operation of integrated circuits, it is important to develop efficient low-cost techniques to detect malicious tampering (also referred to as Hardware Trojan) that causes undesired change in functional behavior. Conventional post- manufacturing testing, test generation algorithms and test coverage metrics cannot be readily extended to hardware Trojan detection. In this paper, we propose a test pattern generation technique based on multiple excitation of rare logic conditions at internal nodes. Such a statistical approach maximizes the probability of inserted Trojans getting triggered and detected by logic testing, while drastically reducing the number of vectors compared to a weighted random pattern based test generation. Moreover, the proposed test generation approach can be effective towards increasing the sensitivity of Trojan detection in existing side-channel approaches that monitor the impact of a Trojan circuit on power or current signature. Simulation results for a set of ISCAS benchmarks show that the proposed test generation approach can achieve comparable or better Trojan detection coverage with about 85% reduction in test length on average over random patterns.},
keywords = {IC Trust Verification},
pubstate = {published},
tppubtype = {inproceedings}
}