Publications

@article{Sengupta2021Facial,

title = {Facial Biometric for Securing Hardware Accelerators},

author = {Anirban Sengupta and Mahendra Rathor},

doi = {10.1109/TVLSI.2020.3029245},

issn = {1557-9999},

year  = {2021},

date = {2021-01-01},

journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},

volume = {29},

number = {1},

pages = {112-123},

abstract = {This article presents a novel facial biometrics-based hardware security methodology to secure hardware accelerators [such as digital signal processing (DSP) and multimedia intellectual property (IP) cores] against ownership threats/IP piracy. In this approach, an IP vendor's facial biometrics is first converted into a corresponding facial signature representing digital template, followed by embedding facial signature's digital template into the design in the form of secret biometric constraints, thereby generating a secured hardware accelerator design. The results report the following qualitative and quantitative analysis of the proposed biometric fingerprint approach: 1) impact of five different facial biometrics constraints on probability of coincidence (Pc) metric (indicating strength of digital evidence). The proposed approach achieves a very low Pc value in the range of 1.54E-5 to 2.01E-5; 2) impact of different facial feature set of a facial biometric image on total number of generated secret constraints and Pc. As evident, for all facial feature sets implemented, Pc ranges between 3.31E-4 and 2.01E-5; and 3) comparative analysis of proposed approach with recent work, for different DSP applications and five different facial biometric images, in terms of Pc. As evident, the proposed approach achieves significantly lower Pc, compared with recent work.},

keywords = {IP Protection},

pubstate = {published},

tppubtype = {article}

}

@article{9129810,

title = {IP Core Steganography Using Switch Based Key-Driven Hash-Chaining and Encoding for Securing DSP Kernels Used in CE Systems},

author = {Mahendra Rathor and Anirban Sengupta},

doi = {10.1109/TCE.2020.3006050},

issn = {1558-4127},

year  = {2020},

date = {2020-08-01},

journal = {IEEE Transactions on Consumer Electronics},

volume = {66},

number = {3},

pages = {251-260},

abstract = {Intellectual property (IP) core of digital signal processing (DSP) kernels act as hardware accelerators in consumer electronics (CE) systems. However due to rising threats of cloning and counterfeiting to an IP core, security remains an important subject of research for these hardware accelerators. This paper presents a novel key-driven hash-chaining based hardware steganography for securing such IP cores used in CE systems. The proposed approach is capable to implant secret invisible stego-marks in design using hash-chaining process that incorporates switches, strong large stego-keys, multiple encoding algorithms and hash blocks. The methodology proposed provides massive security against IP cloning and counterfeiting while incurring nominal design overhead (<; 0.3 %). The results of the proposed approach on comparison with state of the art indicated significantly stronger digital evidence (lower probability of co-incidence), stronger key size (in bits) and lower design cost using proposed stego-marks. Further, from an attacker's perspective, the proposed steganography increases an attacker's effort manifold during decoding the valid stego-key value (for generating/extracting original secret stego-mark), compared to existing approaches.},

keywords = {IP Protection},

pubstate = {published},

tppubtype = {article}

}

@article{Rajarathnam2020,

title = {ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist},

author = {Rachel Selina Rajarathnam and Yibo Lin and Yier Jin and David Z. Pan},

url = {http://cadforassurance.org/wp-content/uploads/rachel2020regds.pdf},

year  = {2020},

date = {2020-01-01},

journal = {Hardware-Oriented Security and Trust (HOST)},

abstract = {With many fabless companies outsourcing integrated circuit (IC) fabrication, the extent of design information recoverable by any third-party foundry remains clouded. While traditional reverse engineering schemes from the layout employ expensive high-resolution imaging techniques to recover design information, the extent of design information that can be recovered by the foundry remains ambiguous. To address this ambiguity, we propose ReGDS, a layout reverse engineering (RE) framework, posing as an inside-foundry attack to acquire original design intent. Our framework uses the layout, in GDSII format, and the technology library to extract the transistor-level connectivity information, and exploits unique relationship-based matching to identify logic gates and thereby, recover the original gate-level netlist. Employing circuits ranging from few hundreds to millions of transistors, we validate the scalability of our framework and demonstrate 100% recovery of the original design from the layout. To further validate the effectiveness of the framework in the presence of obfuscation schemes, we apply ReGDS to layouts of conventional XOR/MUX locked circuits and successfully recover the obfuscated netlist. By applying the Boolean SATisfiability (SAT) attack on the recovered obfuscated netlist, one can recover the entire key and, thereby, retrieve the original design intent. Thus ReGDS results in accelerated acquisition of the gate-level netlist by the attacker, in comparison to imaging-based RE schemes. Our experiments unearth the potential threat of possible intellectual property (IP) piracy at any third-party foundry.},

keywords = {IP Protection},

pubstate = {published},

tppubtype = {article}

}

@article{Sengupta2020Structural,

title = {Structural Obfuscation and Crypto-Steganography-Based Secured JPEG Compression Hardware for Medical Imaging Systems},

author = {Anirban Sengupta and Mahendra Rathor},

doi = {10.1109/ACCESS.2019.2963711},

issn = {2169-3536},

year  = {2020},

date = {2020-01-01},

journal = {IEEE Access},

volume = {8},

pages = {6543-6565},

abstract = {In modern healthcare technology involving diagnosis through medical imaging systems, compression and data transmission play a pivotal role. Medical imaging systems play an indispensable role in several medical applications where camera/scanners generate compressed images about a patient's internal organ and may further transmit it over the internet for remote diagnosis. However, tampered or corrupted compressed medical images may result in wrong diagnosis of diseases leading to fatal consequences. This paper aims to secure the underlying JPEG compression processor used in medical imaging systems that generates the compressed medical images for diagnosis. The proposed work targets to secure the JPEG compression processor against well-acknowledged threats such as counterfeiting/cloning and Trojan insertion using double line of defense through integration of robust structural obfuscation and hardware steganography. The second line of defense incorporates stego-key based hardware steganography that augments the following: non-linear bit manipulation using S-box (confusion property), diffusion property, alphabetic encryption, alphabet substitution, byte concatenation mode, bit-encoding (converting into stego-constraints) and embedding constraints. The results of the proposed approach achieve robust security in terms of significant strength of obfuscation, strong stego-key size (775 bits for JPEG compression processor and 610 bits for JPEG DCT core) and probability of coincidence of 9.89e-8, at nominal design cost.},

keywords = {IP Protection},

pubstate = {published},

tppubtype = {article}

}

@article{Rathor2020Design,

title = {Design Flow of Secured N-Point DFT Application Specific Processor Using Obfuscation and Steganography},

author = {Mahendra Rathor and Anirban Sengupta},

doi = {10.1109/LOCS.2020.2973586},

issn = {2573-9689},

year  = {2020},

date = {2020-01-01},

journal = {IEEE Letters of the Computer Society},

volume = {3},

number = {1},

pages = {13-16},

abstract = {An N-point Discrete Fourier Transform (DFT) has wide application such as speech signal amplitude/phase/frequency spectrum analysis and solving complex numerical problems etc. However a N-point DFT Application Specific Processor (ASP) can be prone to several hardware threats such as reverse engineering, counterfeiting, cloning and fraudulent ownership. This letter proposes a novel design flow of secured N-point DFT application specific processor using high-level transformation based structural obfuscation and crypto-steganography. The proposed design methodology integrates both obfuscation and steganography to yield a robust secured N-point DFT application specific processor design that is capable of achieving 75.28 percent obfuscation at gate-level structure and 99.5 percent enhanced in security w.r.t key-size than recent hardware steganography approach.},

keywords = {IP Protection},

pubstate = {published},

tppubtype = {article}

}

@article{Sengupta2019Crypto,

title = {Crypto-Based Dual-Phase Hardware Steganography for Securing IP cores},

author = {Anirban Sengupta and Mahendra Rathor},

doi = {10.1109/LOCS.2019.2942289},

issn = {2573-9689},

year  = {2019},

date = {2019-12-01},

journal = {IEEE Letters of the Computer Society},

volume = {2},

number = {4},

pages = {32-35},

abstract = {In an untrustworthy foundry, an intellectual property (IP) core is susceptible to piracy. Moreover, an adversary can deceitfully claim the ownership of a pirated IP core. In such cases of ownership conflict, the true ownership of an IP core should be provable. This letter presents a novel approach of securing IP cores against piracy/ false claim of ownership using crypto-based dual phase hardware steganography. By detecting the embedded robust stego-mark in the design, the ownership can be awarded to the genuine IP owner. The paper presents a novel security algorithm that leverages crypto-modules and security properties to generate stego-constraints and embeds them into a hardware IP design during two distinct phases of behavioural synthesis. Because of using large size stego-keys and embedding steganography at two distinct phases, the proposed approach achieves robust security and high reliability than existing recent approaches.},

keywords = {IP Protection},

pubstate = {published},

tppubtype = {article}

}

@article{8854311,

title = {IP Core Steganography for Protecting DSP Kernels Used in CE Systems},

author = {Anirban Sengupta and Mahendra Rathor},

doi = {10.1109/TCE.2019.2944882},

issn = {1558-4127},

year  = {2019},

date = {2019-11-01},

journal = {IEEE Transactions on Consumer Electronics},

volume = {65},

number = {4},

pages = {506-515},

abstract = {Intellectual Property (IP) core protection of Digital Signal Processing (DSP) kernels is an important subject of research for Consumer Electronics (CE) systems. An IP core may be prone to piracy, forgery and counterfeiting. The need of the hour is developing effective technique that is robust and incurs low overhead to detect IP core infringement. This paper presents a novel `IP core steganography' methodology for DSP kernels that is capable of detecting IP piracy. The proposed methodology is capable of implanting concealed information into the existing IP core design of DSP datapath without using any external signature, to reflect the IP core ownership. The presented `IP core steganography' methodology is non-intuitive in nature indicating that the intended secret information does not attract attention to itself from an adversary's perspective. The implanted information incurs almost no design overhead and yields lower design cost than signature-based IP core protection techniques. Further, in the presented approach the amount of concealed information embedded is fully designer controlled through a `thresholding' parameter, unlike signature-based techniques where signature pattern impacts the robustness and overhead. Results of proposed approach yielded lower cost and stronger proof of authorship compared to a signature-based approach.},

keywords = {IP Protection},

pubstate = {published},

tppubtype = {article}

}

@article{8259507,

title = {The Cat and Mouse in Split Manufacturing},

author = {Yujie Wang and Pu Chen and Jiang Hu and Guofeng Li and Jeyavijayan Rajendran},

url = {https://ieeexplore.ieee.org/document/8259507},

doi = {10.1109/TVLSI.2017.2787754},

issn = {1557-9999},

year  = {2018},

date = {2018-05-01},

journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},

volume = {26},

number = {5},

pages = {805-817},

abstract = {Split manufacturing of integrated circuits eliminates vulnerabilities introduced by an untrusted foundry by manufacturing only a part of the target design at an untrusted high-end foundry and the remaining part at a trusted low-end foundry. Most researchers have focused on attack and defenses for hierarchical designs and/or use a relatively high-end trusted foundry, leading to high cost. We propose an attack and defense for split manufacturing for flattened designs. Our attack uses a network-flow model and outperforms previous attacks. We also develop two defense techniques using placement perturbation-one using physical design information and the other using logical information-while considering overhead. The effectiveness of our techniques is demonstrated on benchmark circuits.},

keywords = {IP Protection},

pubstate = {published},

tppubtype = {article}

}

@article{Selsam2018Learning,

title = {Learning a SAT Solver from Single-Bit Supervision},

author = {Daniel Selsam and Matthew Lamm and Benedikt Bünz and Percy Liang and Leonardo de Moura and David L Dill},

url = {http://arxiv.org/abs/1802.03685},

year  = {2018},

date = {2018-01-01},

journal = {CoRR},

volume = {abs/1802.03685},

keywords = {IP Protection},

pubstate = {published},

tppubtype = {article}

}