By: Zhaoxiang Liu, Yier Jin, and Xiaolong Guo Stage: RTL Summary A scalable framework that statically identifies threats in SoC platforms at RT-Level. By parsing HDL into an AST, more information can be used for …
By: Xiaolong Guo and Yier Jin Stage: RTL Summary A framework which evaluates the trustworthiness of a hardware system at register transfer level (RTL). Includes a quantified information flow (QIF) model and extends Verilog/VHDL type …
By: Shih-Yuan Yu (UC Irvine), Rozhin Yasaei (UC Irvine), and Mohammad Abdullah Al Faruque (UC Irvine) Stage: RTL, Gate-Level Summary HW2VEC is an open-source graph learning tool available on GitHub that lowers the threshold for …
By: Tamzidul Hoque (University of Kansas), Mahmudul Hasan (University of Kansas), Jonathan Cruz (University of Florida), Prabuddha Chakraborty (University of Florida), and Swarup Bhunia (University of Florida) Stage: RTL, HDL, Gate-Level, IC Fabrication Summary TReC …
By: Xiaolong Guo and Yier Jin Stage: RTL Summary A comprehensive Proof-Carrying Hardware (PCH) based system level formal solution to evaluate the hardware trust and to further protect the entire hardware and software system. Combines …