By: Jonathan Cruz (University of Florida), Abhishek Nair (IIT Madras), Prabuddha Chakraborty (University of Florida), Tamzidul Hoque (University of Florida), Naren Vikram Raj Masna (University of Florida), and Swarup Bhunia (University of Florida) Stage: Gate-Level …
By: Rozhin Yasaei (UC Irvine), Sina Faezi (UC Irvine), and Mohammad Abdullah Al Faruque (UC Irvine) Stage: IC Fabrication Summary Design and fabrication outsourcing has made integrated circuits vulnerable to malicious modifications by third parties …
By: Tamzidul Hoque (University of Kansas), Mahmudul Hasan (University of Kansas), Jonathan Cruz (University of Florida), Prabuddha Chakraborty (University of Florida), and Swarup Bhunia (University of Florida) Stage: RTL, HDL, Gate-Level, IC Fabrication Summary TReC …
By: Abhishek Nair (IIT Madras), Patanjali SLPSK (University of Florida), Chester Rebeiro (IIT Madras), Swarup Bhunia (University of Florida) Stage: Gate-Level Summary SIGNED is a fully automated commercial quality tool that inserts a watermark in …
By: Embedded Security Group, Max Planck Institute for Security and Privacy, Germany Stage: Gate-Level Summary HAL [/hel/] is a comprehensive netlist reverse engineering and manipulation framework. Virtually all available research on netlist analysis operates on …
By: Yujie Wang (ICT, Chinese Academy of Sciences), Pu Chen (Alexa Shopping, Amazon Web Services), Jiang Hu (Texas A&M University), Guofeng Li (Nankai University), and JV Rajendran (Texas A&M University) Stage: Physical Design and Manufacturing …
By: Rajat Subhra Chakraborty, Francis Wolff, Somnath Paul, Christos Papachristou, and Swarup Bhunia Stage: Production and Test Summary In order to ensure trusted in–field operation of integrated circuits, it is important to develop efficient low–cost …
By: Yuanwen Huang, Swarup Bhunia, and Prabhat Mishra Stage: Production and Test Summary MERS is a statistical test generation tool written in C for generating a corpus of logic test patterns aimed at maximizing the …