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CAD for Assurance
CAD for Assurance of Electronic Systems
MENU
MENU
CAD Tools
Evaluation of Obfuscation
SAIL
SURF
NEOS
SWEEP
SOMA
SCOPE
ObfusGEM
SMT Attack
RANE
RTL Logic Attacks
SnapShot
Fun-SAT
IP/IC Protection
LeGO
ReGDS
Network Flow Attack
ObfusX
KHC-Stego Tool
Crypto-Steganography Tool
SeqL
SATConda
SOFTDEEP
IP Authentication
RTL Locking+Watermarking
KHC-Stego Tool
Crypto-Steganography Tool
Design for Trust
QIF-RTL
IF-Tracker
Formal-PCH
ML Sec. Analysis of Split Mfg.
HW2VEC
QFlow
ML Quant Encoding Attack
Side Channel Analysis
CAD4EM
CAD4EM-RTL
AutoEM
XFC
SAFARI
FEDS
Exp-Fault
DL Model Atks. on Arbiter PUF
HW Troj. Pwr. & EM SC Dataset
PLAN
FORTIFY
System on Chip Analysis
SoC Compiler
DIFTV
IC Trust Verification
MERS
MERO
MIMIC
SIGNED
PCB Trust Verification
PDNPulse
PCBench
TRIT-PCB
Attack Resilience
RowScanner
Def. HMDs vs. Adversarial Atks.
ECP-TRN
Analog Security
CAD4Analog-Capacitor
DHIT
RE & Visualization
NETA
DANA
HAL
Software Assurance
PROMPT
Trust Issues
IP Trojan Attacks
IP Piracy
RTL Trojan Attacks
Extract Design Secrets
IC Trojan Attacks
Overproduction
SCA Attacks
Fault Injection Attacks
Reverse Engineering Attacks
Probing Attacks
Trust Metrics
Trojan Metrics
Benchmarks
Synthetic Trojan Inserted ASIC Benchmarks
Synthetic Trojan Inserted FPGA Benchmarks
Obfuscated Benchmarks: Sequential Obfuscation (ProtectIP)
Security Accelerator or Co-Processor ISA
PCBench
Scalable Attack-Resistant Obfuscation of Logic Circuits (SARO)
SoC Platform
SoC Benchmark
System on Chip Benchmarks
Common Evaluation Platform (CEP)
SoC with Malicious Insertions
Utilities
CAST
Weighted Random Test Generation Tool
Trust Curriculum
HaHa v3.0 Course Materials
HaHa v1.0 Course Materials
Hardware Security Textbook
Publications
Contributors
Faculty
Postdocs
Students
Practitioners
Webmasters
Webinar and Events
Webinars
Contest
Upload Your Tool
Contact Us
Search
Search for:
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CAST: CAD for Security and Trust
Weighted Random Test Generation Tool