CAD for Assurance of Electronic Systems
 

ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist

By: Rachel Selina Rajarathnam, Yibo Lin, Yier Jin, and David Z. Pan

Stage: Layout, Gate-Level netlist

Summary

  • ReGDS is a layout reverse engineering framework posing as an inside-foundry attack to acquire original design intent.
  • The Layout vs Schematic comparison (LVS) tool is used for physical verification, and a graph matching algorithm is used for identifying logic gates.
  • The transistor connection relationship is represented with a novel digital connectivity index (DCI) coding scheme, and thus, recover the original gate-level netlist.
  • By integrating techniques that recover higher-level macro units from the gate-level netlist, ReGDS provides the capability of reverse engineering from the layout to RTL.

Contact

Yier Jin

Input/Output Interface

  • Input: Layout GDSII
  • Output: Gate-level netlist

References

Rajarathnam, Rachel Selina; Lin, Yibo; Jin, Yier; Pan, David Z.

ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist Journal Article

In: Hardware-Oriented Security and Trust (HOST), 2020.

Abstract | Links | BibTeX

Acknowledgments

  • This work was partly supported by DARPA OMG programand NSF (NSF-1812071)