KHC-Stego Tool: Key-Triggered Hash-Chaining Driven Steganography Tool

By: Anirban Sengupta (IIT Indore) and Mahendra Rathor (IIT Indore)

Stage: RTL

Summary

Summary and Threat Model: KHC-Stego tool simulates and analyses the functionality of key-triggered hash-chaining driven steganography approach for securing DSP hardware accelerators against piracy and false claim of ownership threats.

Objective of the tool: The left portion of the tool shows the panel for providing required inputs to the tool, right portion shows the panel with output buttons to see the intermediate and final outputs of the key-triggered hash-chaining based steganography approach. The panel in the middle shows the status of the intermediate steps viz. CDFG scheduling of DSP application, encoding selection, executing hash-chaining process and insert constraints. Initially, these status bars remain red. Upon applying the inputs, the respective status bar turns green. The KHC-Stego tool accepts the DSP application input in the form CDFG along with module library and resource constraints. The tool shows output of intermediate steps of key-triggered hash-chaining based steganography, finally generated stego-constraints, the security metric in terms of probability of coincidence, pre and post-steganography design cost. Further, it also shows scheduling and registers allocation pre and post-embedding steganography constraints, onto the output window. The embedded steganography constraints in the hardware accelerator design can be used as digital evidence to secure against piracy and false claim of ownership threats.

Contact

Dr. Anirban Sengupta and Mahendra Rathor

Input/Output Interface

• Input:
  • Text file of DFG representation of DSP application
  • module library
  • resource constraints (i.e. # adders, multipliers etc.)
  • number of encodings
  • chosen order of encodings
  • stego-key
  • # rounds of hashes
  • constraints size
• Output:
  • Scheduled DFG pre-steganography
  • register allocation table pre-steganography
  • design cost pre-steganography (i.e. baseline cost)
  • scheduled DFG post-steganography
  • register allocation table post-steganography
  • design cost post-steganography phase-1
  • design cost post-steganography phase-2 (final cost)
  • Pc post-steganography phase-1
  • post-steganography phase-2 (final Pc)

Dependencies

OS: Windows 10

References

@book{Sengupta2021Key-triggered,

title = {Key-triggered Hash-chaining based Encoded Hardware Steganography for Securing DSP Hardware Accelerators},

author = {Anirban Sengupta},

isbn = {978-1-83953-306-8},

year  = {2021},

date = {2021-01-01},

keywords = {},

pubstate = {forthcoming},

tppubtype = {book}

}

@article{9129810,

title = {IP Core Steganography Using Switch Based Key-Driven Hash-Chaining and Encoding for Securing DSP Kernels Used in CE Systems},

author = {Mahendra Rathor and Anirban Sengupta},

doi = {10.1109/TCE.2020.3006050},

issn = {1558-4127},

year  = {2020},

date = {2020-08-01},

journal = {IEEE Transactions on Consumer Electronics},

volume = {66},

number = {3},

pages = {251-260},

abstract = {Intellectual property (IP) core of digital signal processing (DSP) kernels act as hardware accelerators in consumer electronics (CE) systems. However due to rising threats of cloning and counterfeiting to an IP core, security remains an important subject of research for these hardware accelerators. This paper presents a novel key-driven hash-chaining based hardware steganography for securing such IP cores used in CE systems. The proposed approach is capable to implant secret invisible stego-marks in design using hash-chaining process that incorporates switches, strong large stego-keys, multiple encoding algorithms and hash blocks. The methodology proposed provides massive security against IP cloning and counterfeiting while incurring nominal design overhead (<; 0.3 %). The results of the proposed approach on comparison with state of the art indicated significantly stronger digital evidence (lower probability of co-incidence), stronger key size (in bits) and lower design cost using proposed stego-marks. Further, from an attacker's perspective, the proposed steganography increases an attacker's effort manifold during decoding the valid stego-key value (for generating/extracting original secret stego-mark), compared to existing approaches.},

keywords = {},

pubstate = {published},

tppubtype = {article}

}

Acknowledgments

• Indian Institute of Technology Indore; Ministry of Electronics & Information Technology (MEitY) Govt. of India; Council of Industrial & Scientific Research (CSIR) -EMR Division