Crypto-Steganography Tool

@article{Sengupta2020Structural,

title = {Structural Obfuscation and Crypto-Steganography-Based Secured JPEG Compression Hardware for Medical Imaging Systems},

author = {Anirban Sengupta and Mahendra Rathor},

doi = {10.1109/ACCESS.2019.2963711},

issn = {2169-3536},

year  = {2020},

date = {2020-01-01},

journal = {IEEE Access},

volume = {8},

pages = {6543-6565},

abstract = {In modern healthcare technology involving diagnosis through medical imaging systems, compression and data transmission play a pivotal role. Medical imaging systems play an indispensable role in several medical applications where camera/scanners generate compressed images about a patient's internal organ and may further transmit it over the internet for remote diagnosis. However, tampered or corrupted compressed medical images may result in wrong diagnosis of diseases leading to fatal consequences. This paper aims to secure the underlying JPEG compression processor used in medical imaging systems that generates the compressed medical images for diagnosis. The proposed work targets to secure the JPEG compression processor against well-acknowledged threats such as counterfeiting/cloning and Trojan insertion using double line of defense through integration of robust structural obfuscation and hardware steganography. The second line of defense incorporates stego-key based hardware steganography that augments the following: non-linear bit manipulation using S-box (confusion property), diffusion property, alphabetic encryption, alphabet substitution, byte concatenation mode, bit-encoding (converting into stego-constraints) and embedding constraints. The results of the proposed approach achieve robust security in terms of significant strength of obfuscation, strong stego-key size (775 bits for JPEG compression processor and 610 bits for JPEG DCT core) and probability of coincidence of 9.89e-8, at nominal design cost.},

keywords = {},

pubstate = {published},

tppubtype = {article}

}

@article{Rathor2020Design,

title = {Design Flow of Secured N-Point DFT Application Specific Processor Using Obfuscation and Steganography},

author = {Mahendra Rathor and Anirban Sengupta},

doi = {10.1109/LOCS.2020.2973586},

issn = {2573-9689},

year  = {2020},

date = {2020-01-01},

journal = {IEEE Letters of the Computer Society},

volume = {3},

number = {1},

pages = {13-16},

abstract = {An N-point Discrete Fourier Transform (DFT) has wide application such as speech signal amplitude/phase/frequency spectrum analysis and solving complex numerical problems etc. However a N-point DFT Application Specific Processor (ASP) can be prone to several hardware threats such as reverse engineering, counterfeiting, cloning and fraudulent ownership. This letter proposes a novel design flow of secured N-point DFT application specific processor using high-level transformation based structural obfuscation and crypto-steganography. The proposed design methodology integrates both obfuscation and steganography to yield a robust secured N-point DFT application specific processor design that is capable of achieving 75.28 percent obfuscation at gate-level structure and 99.5 percent enhanced in security w.r.t key-size than recent hardware steganography approach.},

keywords = {},

pubstate = {published},

tppubtype = {article}

}

@article{Sengupta2019Crypto,

title = {Crypto-Based Dual-Phase Hardware Steganography for Securing IP cores},

author = {Anirban Sengupta and Mahendra Rathor},

doi = {10.1109/LOCS.2019.2942289},

issn = {2573-9689},

year  = {2019},

date = {2019-12-01},

journal = {IEEE Letters of the Computer Society},

volume = {2},

number = {4},

pages = {32-35},

abstract = {In an untrustworthy foundry, an intellectual property (IP) core is susceptible to piracy. Moreover, an adversary can deceitfully claim the ownership of a pirated IP core. In such cases of ownership conflict, the true ownership of an IP core should be provable. This letter presents a novel approach of securing IP cores against piracy/ false claim of ownership using crypto-based dual phase hardware steganography. By detecting the embedded robust stego-mark in the design, the ownership can be awarded to the genuine IP owner. The paper presents a novel security algorithm that leverages crypto-modules and security properties to generate stego-constraints and embeds them into a hardware IP design during two distinct phases of behavioural synthesis. Because of using large size stego-keys and embedding steganography at two distinct phases, the proposed approach achieves robust security and high reliability than existing recent approaches.},

keywords = {},

pubstate = {published},

tppubtype = {article}

}

@article{8854311,

title = {IP Core Steganography for Protecting DSP Kernels Used in CE Systems},

author = {Anirban Sengupta and Mahendra Rathor},

doi = {10.1109/TCE.2019.2944882},

issn = {1558-4127},

year  = {2019},

date = {2019-11-01},

journal = {IEEE Transactions on Consumer Electronics},

volume = {65},

number = {4},

pages = {506-515},

abstract = {Intellectual Property (IP) core protection of Digital Signal Processing (DSP) kernels is an important subject of research for Consumer Electronics (CE) systems. An IP core may be prone to piracy, forgery and counterfeiting. The need of the hour is developing effective technique that is robust and incurs low overhead to detect IP core infringement. This paper presents a novel `IP core steganography' methodology for DSP kernels that is capable of detecting IP piracy. The proposed methodology is capable of implanting concealed information into the existing IP core design of DSP datapath without using any external signature, to reflect the IP core ownership. The presented `IP core steganography' methodology is non-intuitive in nature indicating that the intended secret information does not attract attention to itself from an adversary's perspective. The implanted information incurs almost no design overhead and yields lower design cost than signature-based IP core protection techniques. Further, in the presented approach the amount of concealed information embedded is fully designer controlled through a `thresholding' parameter, unlike signature-based techniques where signature pattern impacts the robustness and overhead. Results of proposed approach yielded lower cost and stronger proof of authorship compared to a signature-based approach.},

keywords = {},

pubstate = {published},

tppubtype = {article}

}