By: Yinghua Hu (University of Southern California), Yuke Zhang (University of Southern California), Kaixin Yang (University of Southern California), Dake Chen (University of Southern California), Peter A. Beerel (University of Southern California), and Pierluigi Nuzzo …
By: Shih-Yuan Yu (UC Irvine), Rozhin Yasaei (UC Irvine), and Mohammad Abdullah Al Faruque (UC Irvine) Stage: RTL, Gate-Level Summary HW2VEC is an open-source graph learning tool available on GitHub that lowers the threshold for …
By: A V Lakshmy (IIT Madras), Chester Rebeiro (IIT Madras), and Swarup Bhunia (University of Florida) Stage: RTL, HDL, Gate-Level Summary FORTIFY is an analytical framework that can efficiently estimate the fine-grained power side-channel leakage …
By: Muhammad Arsath K F (IIT Madras), Vinod Ganesan (IIT Madras), Rahul Bodduna (IIT Madras), and Chester Rebeiro (IIT Madras) Stage: RTL, HDL, Gate-Level Summary PLAN (Power attack Leakage ANalyzer) performs power side-channel analysis of …
By: Lennart Reimann (RWTH Aachen University), Luca Hanel (RWTH Aachen University), Dominik Sisejkovic (RWTH Aachen University), Farhad Merchant (RWTH Aachen University), and Rainer Leupers (RWTH Aachen University) Stage: RTL Summary A tool that detects hardware …
By: Embedded Security Group, Max Planck Institute for Security and Privacy, Germany Stage: Gate-Level Summary HAL [/hel/] is a comprehensive netlist reverse engineering and manipulation framework. Virtually all available research on netlist analysis operates on …
By: Tuba Yavuz (University of Florida) and Ken (Yihang) Bai (University of Florida) Stage: Software Design and Development Summary PROMPT performs component-level analysis using API model guided symbolic execution. API models can be specified using …