CAD for Assurance of Electronic Systems
 

ObfusGEM

By: Michael Zuzak (University of Maryland, College Park) and Ankur Srivastava (University of Maryland, College Park) Stage: RTL, HDL Summary ObfusGEM is a comprehensive logic locking simulator designed to evaluate the supply-chain security of locked …

SATConda

By: Rakibul Hassan (George Mason University), Gaurav Kohle (UC Davis), Setareh Rafatirad (UC Davis), Houman Homayoun (UC Davis), and Sai Manoj Pudukotai Dinakarrao (George Mason University) Stage: Gate-Level Summary We propose a neural network-based cognitive …

SnapShot

By: Dominik Sisejkovic (RWTH Aachen University), Farhad Merchant (RWTH Aachen University), Lennart M. Reimann (RWTH Aachen University), Harshit Srivastava (RWTH Aachen University), Ahmed Hallawa (RWTH Aachen University) and Rainer Leupers (RWTH Aachen University) Stage: RTL, …

RTL Logic Attacks

By: Chandan Karfa (IIT Guwahati) and Ramanuj Chouksey (IIT Guwahati) Stage: RTL Summary An attack on locked RTL generated by TAO a state-of-the-art RTL locking solution. Contact Chandan Karfa Ramanuj Chouksey Input/Output Interface Input: Locked …

HAL

By: Embedded Security Group, Max Planck Institute for Security and Privacy, Germany Stage: Gate-Level Summary HAL [/hel/] is a comprehensive netlist reverse engineering and manipulation framework. Virtually all available research on netlist analysis operates on …