Scalable Attack-Resistant Obfuscation of Logic Circuits (SARO)

@misc{mitlincolnlaboratory,

title = {Common Evaluation Platform (CEP)},

author = {MIT-LL},

url = {https://github.com/mit-ll/CEP},

year  = {2020},

date = {2020-01-01},

journal = {GitHub},

abstract = {The Common Evaluation Platform (CEP) is intended as a surrogate System on a Chip (SoC) allowing users to test a variety of tools and techniques. Test vectors are provided to ensure the underlying functionality is maintained even after modification.



Additional information on the objectives of the CEP may be found in ./CEP_SecEvalTargets.pdf.



The CEP is based on the SiFive U500 Platform which leverages the UCB Rocket Chip. Much of the design is described in Chisel (https://github.com/freechipsproject/chisel3), a domain specific extension to Scala tailored towards constructing hardware. The output of the Chisel generators is synthesizable verilog.



Currently, the test platform for the CEP is the Xilinx VC-707 FPGA Development Board. Longer term plans include migrating to other platforms with the eventual goal of taping out an ASIC.},

keywords = {},

pubstate = {published},

tppubtype = {misc}

}

@misc{alaql2020scalable,

title = {Scalable Attack-Resistant Obfuscation of Logic Circuits},

author = {Abdulrahman Alaql and Swarup Bhunia},

url = {https://arxiv.org/abs/2010.15329},

year  = {2020},

date = {2020-01-01},

keywords = {},

pubstate = {published},

tppubtype = {misc}

}