Description
Side-Channel Attacks (SCAs) exploit emissions from integrated circuits (ICs), which can be in the form of electromagnetic radiations, sound, light, power consumption, and/or timing information. Since, its inception many SCAs have been developed such as audio-based attacks, cache and timing attacks, power monitoring attacks, electromagnetic emission monitoring attacks, data remanence, software-initiated fault-attacks, optical attacks, and differential-fault analysis. These attacks exploit vulnerabilities in the ICs of the Internet of Things (IoT) devices, mobile devices, smart cards, and computers to infer sensitive information. The new era of billions of personal devices and new technologies such as cloud computing are enabling newer SCAs such as cache-timing attacks or DRAM row-buffer attacks, which can be carried out remotely by executing malicious code in the targeted cloud environment. Existing architectural and circuit level solutions for preventing SCAs in ICs result in significant area and power overhead. Furthermore, the design optimization process of existing computer-aided design (CAD) tools results in side-channel leakage. As such, new CAD tools are needed that incorporates security measures to prevent side-channel leakage in ICs. Consequently, tools such as CAD4EM-Placement, CAD4EM-RTL, AutoEM, CAD4Power-FPGA, XFC, FEDS, and SAFARI have been developed to address SCA concerns.
Related Tools
- FORTIFY
- PLAN
- Hardware Trojan Power & EM Side-Channel Dataset
- DHIT: Defense of High-Speed Transceivers
- Deep Learning Based Model Building Attacks on Arbiter PUF Compositions
- AutoEM
- FEDS: Comprehensive Fault Attack Exploitability Detection for Software Implementations of Block Ciphers
- SAFARI: Automatic Synthesis of Fault-Attack Resistant Block Cipher Implementations
- XFC: eXploitable Fault Characterization
- CAD4EM-RTL: CAD for EM Security through RTL Quantitative Assessment
- CAD4EM-P: CAD for EM Security-Placement
Publications
K, Keerthi; Roy, Indrani; Rebeiro, Chester; Hazra, Aritra; Bhunia, Swarup
FEDS: Comprehensive Fault Attack Exploitability Detection for Software Implementations of Block Ciphers Journal Article
In: IACR Transactions on Cryptographic Hardware and Embedded Systems, vol. 2020, no. 2, pp. 272-299, 2020.
@article{Keerthi2020,
title = {FEDS: Comprehensive Fault Attack Exploitability Detection for Software Implementations of Block Ciphers},
author = {Keerthi K and Indrani Roy and Chester Rebeiro and Aritra Hazra and Swarup Bhunia},
url = {https://tches.iacr.org/index.php/TCHES/article/view/8552},
doi = {https://doi.org/10.13154/tches.v2020.i2.272-299},
year = {2020},
date = {2020-03-02},
journal = {IACR Transactions on Cryptographic Hardware and Embedded Systems},
volume = {2020},
number = {2},
pages = { 272-299},
abstract = {Fault injection attacks are one of the most powerful forms of cryptanalytic attacks on ciphers. A single precisely injected fault during the execution of a cipher like the AES, can completely reveal the key within a few milliseconds. Software implementations of ciphers, therefore, need to be thoroughly evaluated for such attacks. In recent years, automated tools have been developed to perform these evaluations. These tools either work on the cipher algorithm or on their implementations. Tools that work at the algorithm level can provide a comprehensive assessment of fault attack vulnerability for different fault attacks and with different fault models. Their application is, however, restricted because every realization of the cipher has unique vulnerabilities. On the other hand, tools that work on cipher implementations have a much wider application but are often restricted by the range of fault attacks and the number of fault models they can evaluate.
In this paper, we propose a framework, called FEDS, that uses a combination of compiler techniques and model checking to merge the advantages of both, algorithmic level tools as well as implementation level tools. Like the algorithmic level tools, FEDS can provide a comprehensive assessment of fault attack exploitability considering a wide range of fault attacks and fault models. Like implementation level tools, FEDS works with implementations, therefore has wide applications. We demonstrate the versatility of FEDS by evaluating seven different implementations of AES (including bitsliced implementation) and implementations of CLEFIA and CAMELLIA for Differential Fault Attacks. The framework automatically identifies exploitable instructions in all implementations. Further, we present an application of FEDS in a Fault Attack Aware Compiler, that can automatically identify and protect exploitable regions of the code. We demonstrate that the compiler can generate significantly more efficient code than a naïvely protected equivalent while maintaining the same level of protection.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Fault injection attacks are one of the most powerful forms of cryptanalytic attacks on ciphers. A single precisely injected fault during the execution of a cipher like the AES, can completely reveal the key within a few milliseconds. Software implementations of ciphers, therefore, need to be thoroughly evaluated for such attacks. In recent years, automated tools have been developed to perform these evaluations. These tools either work on the cipher algorithm or on their implementations. Tools that work at the algorithm level can provide a comprehensive assessment of fault attack vulnerability for different fault attacks and with different fault models. Their application is, however, restricted because every realization of the cipher has unique vulnerabilities. On the other hand, tools that work on cipher implementations have a much wider application but are often restricted by the range of fault attacks and the number of fault models they can evaluate.
In this paper, we propose a framework, called FEDS, that uses a combination of compiler techniques and model checking to merge the advantages of both, algorithmic level tools as well as implementation level tools. Like the algorithmic level tools, FEDS can provide a comprehensive assessment of fault attack exploitability considering a wide range of fault attacks and fault models. Like implementation level tools, FEDS works with implementations, therefore has wide applications. We demonstrate the versatility of FEDS by evaluating seven different implementations of AES (including bitsliced implementation) and implementations of CLEFIA and CAMELLIA for Differential Fault Attacks. The framework automatically identifies exploitable instructions in all implementations. Further, we present an application of FEDS in a Fault Attack Aware Compiler, that can automatically identify and protect exploitable regions of the code. We demonstrate that the compiler can generate significantly more efficient code than a naïvely protected equivalent while maintaining the same level of protection.
In this paper, we propose a framework, called FEDS, that uses a combination of compiler techniques and model checking to merge the advantages of both, algorithmic level tools as well as implementation level tools. Like the algorithmic level tools, FEDS can provide a comprehensive assessment of fault attack exploitability considering a wide range of fault attacks and fault models. Like implementation level tools, FEDS works with implementations, therefore has wide applications. We demonstrate the versatility of FEDS by evaluating seven different implementations of AES (including bitsliced implementation) and implementations of CLEFIA and CAMELLIA for Differential Fault Attacks. The framework automatically identifies exploitable instructions in all implementations. Further, we present an application of FEDS in a Fault Attack Aware Compiler, that can automatically identify and protect exploitable regions of the code. We demonstrate that the compiler can generate significantly more efficient code than a naïvely protected equivalent while maintaining the same level of protection.
He, Jiaji; Ma, Haocheng; Guo, Xiaolong; Zhao, Yiqiang; Jin, Yier
Design for EM Side-Channel Security through Quantitative Assessment of RTL Implementations Proceedings Article
In: 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 62-67, IEEE, Beijing, China , 2020.
@inproceedings{He2020,
title = {Design for EM Side-Channel Security through Quantitative Assessment of RTL Implementations},
author = {Jiaji He and Haocheng Ma and Xiaolong Guo and Yiqiang Zhao and Yier Jin },
url = {http://cadforassurance.org/wp-content/uploads/jiaji2020design.pdf},
doi = {10.1109/ASP-DAC47756.2020.9045426},
year = {2020},
date = {2020-01-13},
booktitle = {2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)},
pages = {62-67},
publisher = {IEEE},
address = {Beijing, China },
abstract = {Electromagnetic (EM) side-channel attacks aim at extracting secret information from cryptographic hardware implementations. Countermeasures have been proposed at the device level, register-transfer level (RTL), and layout level, though efficient, there are still requirements for quantitative assessment of the hardware implementations' resistance against EM side-channel attacks. In this paper, we propose a design for EM side-channel security evaluation and optimization framework based on the t-test evaluation results derived from RTL hardware implementations. Different implementations of the same cryptographic algorithm are evaluated under different hypothesis leakage models considering the driven capabilities of logic components, and the evaluation results are validated with side-channel attacks on FPGA platform. Experimental results prove the feasibility of the proposed side-channel leakage evaluation method at the pre-silicon stage. The remedies and suggested security design rules are also discussed.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Electromagnetic (EM) side-channel attacks aim at extracting secret information from cryptographic hardware implementations. Countermeasures have been proposed at the device level, register-transfer level (RTL), and layout level, though efficient, there are still requirements for quantitative assessment of the hardware implementations' resistance against EM side-channel attacks. In this paper, we propose a design for EM side-channel security evaluation and optimization framework based on the t-test evaluation results derived from RTL hardware implementations. Different implementations of the same cryptographic algorithm are evaluated under different hypothesis leakage models considering the driven capabilities of logic components, and the evaluation results are validated with side-channel attacks on FPGA platform. Experimental results prove the feasibility of the proposed side-channel leakage evaluation method at the pre-silicon stage. The remedies and suggested security design rules are also discussed.
Ma, Haocheng; He, Jiaji; Liu, Yanjiang; Zhao, Yiqiang; Jin, Yier
CAD4EM-P: Security-Driven Placement Tools for Electromagnetic Side Channel Protection Proceedings Article
In: 2019 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), pp. 1-6, IEEE, Xi'an, P.R. China, 2019.
@inproceedings{Ma2019,
title = {CAD4EM-P: Security-Driven Placement Tools for Electromagnetic Side Channel Protection},
author = {Haocheng Ma and Jiaji He and Yanjiang Liu and Yiqiang Zhao and Yier Jin},
url = {http://cadforassurance.org/wp-content/uploads/haocheng1019cad4emp.pdf},
doi = {10.1109/AsianHOST47458.2019.9006705},
year = {2019},
date = {2019-12-16},
booktitle = {2019 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)},
pages = {1-6},
publisher = {IEEE},
address = {Xi'an, P.R. China},
abstract = {Side-Channel Analysis (SCA) attacks are major threats to hardware security. Upon this security threat, various countermeasures at different design layers have been proposed against SCA attacks. These approaches often introduce significant performance overheads and impose high requirements of side-channel security backgrounds to IC designers. In this paper, we propose an automatic computer-aided design (CAD) tool that can enhance the circuit resistance against electromagnetic (EM) SCA attacks. This new tool will guide a security-driven placement process and can be seamlessly integrated into the modern IC design flow. The protected IC design will be resilient to SCA attacks with the negligible area and power overheads. In order to develop this tool, we first investigate the root-cause of EM leakage at the layout level and mathematically demonstrate the feasibility of security-driven placement through the EM leakage modeling. We then identify that the correlation between the data under the protection and the EM leakage can be significantly reduced through a data-dependent register's reallocation. Simulation results on cryptographic circuits prove the effectiveness of both the constructed EM leakage model and the EM model-based CAD tool for EM security.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Side-Channel Analysis (SCA) attacks are major threats to hardware security. Upon this security threat, various countermeasures at different design layers have been proposed against SCA attacks. These approaches often introduce significant performance overheads and impose high requirements of side-channel security backgrounds to IC designers. In this paper, we propose an automatic computer-aided design (CAD) tool that can enhance the circuit resistance against electromagnetic (EM) SCA attacks. This new tool will guide a security-driven placement process and can be seamlessly integrated into the modern IC design flow. The protected IC design will be resilient to SCA attacks with the negligible area and power overheads. In order to develop this tool, we first investigate the root-cause of EM leakage at the layout level and mathematically demonstrate the feasibility of security-driven placement through the EM leakage modeling. We then identify that the correlation between the data under the protection and the EM leakage can be significantly reduced through a data-dependent register's reallocation. Simulation results on cryptographic circuits prove the effectiveness of both the constructed EM leakage model and the EM model-based CAD tool for EM security.
Roy, Indrani; Rebeiro, Chester; Hazra, Aritra; Bhunia, Swarup
SAFARI: Automatic Synthesis of Fault-Attack Resistant Block Cipher Implementations Journal Article
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 4, pp. 752-765, 2019, ISBN: 19545508.
@article{Roy2019,
title = {SAFARI: Automatic Synthesis of Fault-Attack Resistant Block Cipher Implementations},
author = {Indrani Roy and Chester Rebeiro and Aritra Hazra and Swarup Bhunia},
url = {https://ieeexplore.ieee.org/document/8634921},
doi = {10.1109/TCAD.2019.2897629},
isbn = {19545508},
year = {2019},
date = {2019-12-01},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
volume = {39},
number = {4},
pages = {752-765},
abstract = {Most cipher implementations are vulnerable to a class of cryptanalytic attacks known as fault injection attacks. To reveal the secret key, these attacks make use of faults induced at specific locations during the execution of the cipher. Countermeasures for fault injection attacks require these vulnerable locations in the implementation to be first identified and then protected. However, both these steps are difficult and error-prone and, hence, it requires considerable expertise to design efficient countermeasures. Incorrect or insufficient application of the countermeasures would cause the implementation to remain vulnerable, while inefficient application of the countermeasures could lead to significant performance penalties to achieve the desired fault-attack resistance. In this paper, we present a novel framework called SAFARI for automatically synthesizing fault-attack resistant implementations of block ciphers. The framework takes as input the security requirements and a high-level specification of the block cipher. It automatically detects the vulnerable locations from the specification, applies an appropriate countermeasure based on the user-specified security requirements, and then synthesizes an efficient, fault-attack protected, RTL, or C code for the cipher. We take AES, CAMELLIA, and CLEFIA as case studies and demonstrate how the framework would explore different countermeasures, based on the vulnerability of the locations, the output format, and the required security margins. We then evaluate the efficacy of SAFARI in hardware and software to the design overhead incurred and the fault coverage.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
Most cipher implementations are vulnerable to a class of cryptanalytic attacks known as fault injection attacks. To reveal the secret key, these attacks make use of faults induced at specific locations during the execution of the cipher. Countermeasures for fault injection attacks require these vulnerable locations in the implementation to be first identified and then protected. However, both these steps are difficult and error-prone and, hence, it requires considerable expertise to design efficient countermeasures. Incorrect or insufficient application of the countermeasures would cause the implementation to remain vulnerable, while inefficient application of the countermeasures could lead to significant performance penalties to achieve the desired fault-attack resistance. In this paper, we present a novel framework called SAFARI for automatically synthesizing fault-attack resistant implementations of block ciphers. The framework takes as input the security requirements and a high-level specification of the block cipher. It automatically detects the vulnerable locations from the specification, applies an appropriate countermeasure based on the user-specified security requirements, and then synthesizes an efficient, fault-attack protected, RTL, or C code for the cipher. We take AES, CAMELLIA, and CLEFIA as case studies and demonstrate how the framework would explore different countermeasures, based on the vulnerability of the locations, the output format, and the required security margins. We then evaluate the efficacy of SAFARI in hardware and software to the design overhead incurred and the fault coverage.
Santikellur, Pranesh; Bhattacharyay, Aritra; Chakraborty, Rajat Subhra
Deep Learning based Model Building Attacks on Arbiter PUF Compositions Miscellaneous
Cryptology ePrint Archive, Report 2019/566, 2019.
@misc{Santikellur2019,
title = {Deep Learning based Model Building Attacks on Arbiter PUF Compositions},
author = {Pranesh Santikellur and Aritra Bhattacharyay and Rajat Subhra Chakraborty},
url = {https://eprint.iacr.org/2019/566.pdf},
year = {2019},
date = {2019-01-01},
abstract = {Robustness to modeling attacks is an important requirement for PUF circuits. Several reported Arbiter PUF compositions have resisted modeling attacks. and often require huge computational resources for successful modeling. In this paper we present deep feedforward neural network based modeling attack on 64-bit and 128-bit Arbiter PUF (APUF), and several other PUFs composed of Arbiter PUFs, namely, XOR APUF, Lightweight Secure PUF (LSPUF), Multiplexer PUF (MPUF) and its variants (cMPUF and rMPUF), and the recently proposed Interpose PUF (IPUF, up to the (4,4)-IPUF configuration). The technique requires no auxiliary information (e.g. side-channel information or reliability information), while employing deep neural networks of relatively low structural complexity to achieve very high modeling accuracy at low computational overhead (compared to previously proposed approaches), and is reasonably robust to error-inflicted training dataset.},
howpublished = {Cryptology ePrint Archive, Report 2019/566},
keywords = {},
pubstate = {published},
tppubtype = {misc}
}
Robustness to modeling attacks is an important requirement for PUF circuits. Several reported Arbiter PUF compositions have resisted modeling attacks. and often require huge computational resources for successful modeling. In this paper we present deep feedforward neural network based modeling attack on 64-bit and 128-bit Arbiter PUF (APUF), and several other PUFs composed of Arbiter PUFs, namely, XOR APUF, Lightweight Secure PUF (LSPUF), Multiplexer PUF (MPUF) and its variants (cMPUF and rMPUF), and the recently proposed Interpose PUF (IPUF, up to the (4,4)-IPUF configuration). The technique requires no auxiliary information (e.g. side-channel information or reliability information), while employing deep neural networks of relatively low structural complexity to achieve very high modeling accuracy at low computational overhead (compared to previously proposed approaches), and is reasonably robust to error-inflicted training dataset.
Takarabt, Sofiane; Schaub, Alexander; Facon, Adrien; Guilley, Sylvain; Sauvage, Laurent; Souissi, Youssef; Mathieu, Yves
Cache-Timing Attacks Still Threaten IoT Devices Proceedings Article
In: Codes, Cryptology and Information Security, pp. 13–30, Springer International Publishing, Cham, 2019, ISBN: 978-3-030-16458-4.
@inproceedings{Takarabt2019Cache,
title = {Cache-Timing Attacks Still Threaten IoT Devices},
author = {Sofiane Takarabt and Alexander Schaub and Adrien Facon and Sylvain Guilley and Laurent Sauvage and Youssef Souissi and Yves Mathieu},
doi = {10.1007/978-3-030-16458-4_2},
isbn = {978-3-030-16458-4},
year = {2019},
date = {2019-01-01},
booktitle = {Codes, Cryptology and Information Security},
pages = {13--30},
publisher = {Springer International Publishing},
address = {Cham},
abstract = {Deployed widely and embedding sensitive data, The security of IoT devices depend on the reliability of cryptographic libraries to protect user information. However when implemented on real systems, cryptographic algorithms are vulnerable to side-channel attacks based on their execution behavior, which can be revealed by measurements of physical quantities such as timing or power consumption. Some countermeasures can be implemented in order to prevent those attacks. However those countermeasures are generally designed at high level description, and when implemented, some residual leakage may persist. In this article we propose a methodology to assess the robustness of the MbedTLS library against timing and cache-timing attacks. This comprehensive study of side-channel security allows us to identify the most frequent weaknesses in software cryptographic code and how those might be fixed. This methodology checks the whole source code, from the top level routines to low level primitives, that are used for the final application. We retrieve hundreds of lines of code that leak sensitive information.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Deployed widely and embedding sensitive data, The security of IoT devices depend on the reliability of cryptographic libraries to protect user information. However when implemented on real systems, cryptographic algorithms are vulnerable to side-channel attacks based on their execution behavior, which can be revealed by measurements of physical quantities such as timing or power consumption. Some countermeasures can be implemented in order to prevent those attacks. However those countermeasures are generally designed at high level description, and when implemented, some residual leakage may persist. In this article we propose a methodology to assess the robustness of the MbedTLS library against timing and cache-timing attacks. This comprehensive study of side-channel security allows us to identify the most frequent weaknesses in software cryptographic code and how those might be fixed. This methodology checks the whole source code, from the top level routines to low level primitives, that are used for the final application. We retrieve hundreds of lines of code that leak sensitive information.
Carré, Sébastien; Facon, Adrien; Guilley, Sylvain; Takarabt, Sofiane; Schaub, Alexander; Souissi, Youssef
Cache-Timing Attack Detection and Prevention Proceedings Article
In: Constructive Side-Channel Analysis and Secure Design, pp. 13–21, Springer International Publishing, Cham, 2019, ISBN: 978-3-030-16350-1.
@inproceedings{Carre2019Cache,
title = {Cache-Timing Attack Detection and Prevention},
author = {Sébastien Carré and Adrien Facon and Sylvain Guilley and Sofiane Takarabt and Alexander Schaub and Youssef Souissi},
doi = {10.1007/978-3-030-16350-1_2},
isbn = {978-3-030-16350-1},
year = {2019},
date = {2019-01-01},
booktitle = {Constructive Side-Channel Analysis and Secure Design},
pages = {13--21},
publisher = {Springer International Publishing},
address = {Cham},
abstract = {With the publication of Spectre & Meltdown attacks, cache-timing exploitation techniques have received a wealth of attention recently. On the one hand, it is now well understood which patterns in the source code create observable unbalances in terms of timing. On the other hand, some practical attacks have also been reported. But the exact relation between vulnerabilities and exploitations is not enough studied as of today. In this article, we put forward a methodology to characterize the leakage induced by a ``non-constant-time'' construct in the source code. This methodology allows us to recover known attacks and to warn about possible new ones, possibly devastating.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
With the publication of Spectre & Meltdown attacks, cache-timing exploitation techniques have received a wealth of attention recently. On the one hand, it is now well understood which patterns in the source code create observable unbalances in terms of timing. On the other hand, some practical attacks have also been reported. But the exact relation between vulnerabilities and exploitations is not enough studied as of today. In this article, we put forward a methodology to characterize the leakage induced by a ``non-constant-time'' construct in the source code. This methodology allows us to recover known attacks and to warn about possible new ones, possibly devastating.
Bruneau, Nicolas; Christen, Charles; Danger, Jean-Luc; Facon, Adrien; Guilley, Sylvain
Security Evaluation Against Side-Channel Analysis at Compilation Time Proceedings Article
In: pp. 129–148, Springer International Publishing, Cham, 2019, ISBN: 978-3-030-36237-9.
@inproceedings{Bruneau2019security,
title = {Security Evaluation Against Side-Channel Analysis at Compilation Time},
author = {Nicolas Bruneau and Charles Christen and Jean-Luc Danger and Adrien Facon and Sylvain Guilley},
doi = {10.1007/978-3-030-36237-9_8},
isbn = {978-3-030-36237-9},
year = {2019},
date = {2019-01-01},
pages = {129--148},
publisher = {Springer International Publishing},
address = {Cham},
abstract = {Masking countermeasure is implemented to thwart side-channel attacks. The maturity of high-order masking schemes has reached the level where the concepts are sound and proven. For instance, Rivain and Prouff proposed a full-fledged AES at CHES 2010. Some non-trivial fixes regarding refresh functions were needed though. Now, industry is adopting such solutions, and for the sake of both quality and certification requirements, masked cryptographic code shall be checked for correctness using the same model as that of the theoretical protection rationale (for instance the probing leakage model).},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Masking countermeasure is implemented to thwart side-channel attacks. The maturity of high-order masking schemes has reached the level where the concepts are sound and proven. For instance, Rivain and Prouff proposed a full-fledged AES at CHES 2010. Some non-trivial fixes regarding refresh functions were needed though. Now, industry is adopting such solutions, and for the sake of both quality and certification requirements, masked cryptographic code shall be checked for correctness using the same model as that of the theoretical protection rationale (for instance the probing leakage model).
Facon, Adrien; Guilley, Sylvain; Lec'hvien, Matthieu; Marion, Damien; Perianin, Thomas
Binary Data Analysis for Source Code Leakage Assessment Proceedings Article
In: Innovative Security Solutions for Information Technology and Communications, pp. 391–409, Springer International Publishing, Cham, 2019, ISBN: 978-3-030-12942-2.
@inproceedings{10.1007/978-3-030-12942-2_30,
title = {Binary Data Analysis for Source Code Leakage Assessment},
author = {Adrien Facon and Sylvain Guilley and Matthieu Lec'hvien and Damien Marion and Thomas Perianin},
doi = {10.1007/978-3-030-12942-2_30},
isbn = {978-3-030-12942-2},
year = {2019},
date = {2019-01-01},
booktitle = {Innovative Security Solutions for Information Technology and Communications},
pages = {391--409},
publisher = {Springer International Publishing},
address = {Cham},
abstract = {Side Channel Analysis (SCA) is known to be a serious threat for cryptographic algorithms since twenty years. Recently, the explosion of the Internet of Things (IoT) has increased the number of devices that can be targeted by these attacks, making this threat more relevant than ever. Furthermore, the evaluations of cryptographic algorithms regarding SCA are usually performed at the very end of a product design cycle, impacting considerably the time-to-market in case of security flaws. Hence, early simulations of embedded software and methodologies have been developed to assess vulnerabilities with respect to SCA for specific hardware architectures. Aiming to provide an agnostic evaluation method, we propose in this paper a new methodology of data collection and analysis to reveal leakage of sensitive information from any software implementation. As an illustration our solution is used interestingly to break a White Box Cryptography (WBC) implementation, challenging existing simulation-based attacks.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Side Channel Analysis (SCA) is known to be a serious threat for cryptographic algorithms since twenty years. Recently, the explosion of the Internet of Things (IoT) has increased the number of devices that can be targeted by these attacks, making this threat more relevant than ever. Furthermore, the evaluations of cryptographic algorithms regarding SCA are usually performed at the very end of a product design cycle, impacting considerably the time-to-market in case of security flaws. Hence, early simulations of embedded software and methodologies have been developed to assess vulnerabilities with respect to SCA for specific hardware architectures. Aiming to provide an agnostic evaluation method, we propose in this paper a new methodology of data collection and analysis to reveal leakage of sensitive information from any software implementation. As an illustration our solution is used interestingly to break a White Box Cryptography (WBC) implementation, challenging existing simulation-based attacks.
Souissi, Youssef; Facon, Adrien; Guilley, Sylvain
Virtual Security Evaluation Proceedings Article
In: Carlet, Claude; Guilley, Sylvain; Nitaj, Abderrahmane; Souidi, El Mamoun (Ed.): Codes, Cryptology and Information Security, pp. 3–12, Springer International Publishing, Cham, 2019, ISBN: 978-3-030-16458-4.
@inproceedings{Souissi2019Virtual,
title = {Virtual Security Evaluation},
author = {Youssef Souissi and Adrien Facon and Sylvain Guilley},
editor = {Claude Carlet and Sylvain Guilley and Abderrahmane Nitaj and El Mamoun Souidi},
doi = {10.1007/978-3-030-16458-4_1},
isbn = {978-3-030-16458-4},
year = {2019},
date = {2019-01-01},
booktitle = {Codes, Cryptology and Information Security},
pages = {3--12},
publisher = {Springer International Publishing},
address = {Cham},
abstract = {``An ounce of prevention is worth a pound of cure''. This paper presents a methodology to detect side-channel leakage at source-code level. It leverages simple tests performed on noise-less traces of execution, and returns to the developer accurate information about the security issues. The feedback is in terms of location (where in code, when in time), in terms of security severity (amount and duration of leakage), and most importantly, in terms of possible reason for the leakage. After the source code (and subsequently the compiled code) has been sanitized, attack attempts complement the methodology to test the implementation against realistic exploitations. This last steps allows to validate whether the tolerated leakages during the sanitizing stage are indeed benign.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
``An ounce of prevention is worth a pound of cure''. This paper presents a methodology to detect side-channel leakage at source-code level. It leverages simple tests performed on noise-less traces of execution, and returns to the developer accurate information about the security issues. The feedback is in terms of location (where in code, when in time), in terms of security severity (amount and duration of leakage), and most importantly, in terms of possible reason for the leakage. After the source code (and subsequently the compiled code) has been sanitized, attack attempts complement the methodology to test the implementation against realistic exploitations. This last steps allows to validate whether the tolerated leakages during the sanitizing stage are indeed benign.
Mathieu, Brandon L.; McCue, Jamin J.; Duncan, Lucas; Dupaix, Brian; Lavasani, Hossein Miri; Khalil, Waleed
A Capacitively Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver Journal Article
In: IEEE Journal of Solid-State Circuits, vol. 53, no. 9, pp. 2500-2511, 2018, ISSN: 1558-173X.
@article{mathieu2018cap,
title = {A Capacitively Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver},
author = {Brandon L. Mathieu and Jamin J. McCue and Lucas Duncan and Brian Dupaix and Hossein Miri Lavasani and Waleed Khalil},
doi = {10.1109/JSSC.2018.2859390},
issn = {1558-173X},
year = {2018},
date = {2018-09-01},
journal = {IEEE Journal of Solid-State Circuits},
volume = {53},
number = {9},
pages = {2500-2511},
abstract = {A power and area efficient, capacitively coupled receiver for short links is presented. The proposed architecture enables a wide input common-mode range by utilizing on-chip ac-coupling capacitors, which avoids the use of large, off-chip capacitors or slow, rail-to-rail input stages. The small coupling capacitance and bias switches generate a pseudo return-to-zero pulse that is latched into the receiver via digital feedback. This input latching reduces the effects of baseline wander caused by unbalanced data streams without the need for encoding or scrambling. In addition, the full-scale digital feedback is used as the receiver output, enabling direct interface with standard digital cells. The architecture is implemented in a 130-nm SiGe BiCMOS and 45-nm CMOS silicon-on-insulator (SOI) technology. The 130-nm SiGe BiCMOS design achieves a peak data rate of 10 Gb/s at 5.1 mW, while a peak efficiency of 0.46 mW/Gb/s is recorded at 8 Gb/s. The 45-nm CMOS SOI design achieves a peak data rate of 30 Gb/s at 12.02 mW, with a peak efficiency of 0.24 mW/Gb/s at 25 Gb/s. Both the SiGe BiCMOS and CMOS SOI designs exhibit BERs of <;10-12 with PRBS15 data as small as 100 mV and occupy 0.012 and 0.007 mm2, respectively, including the on-chip coupling capacitance.},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
A power and area efficient, capacitively coupled receiver for short links is presented. The proposed architecture enables a wide input common-mode range by utilizing on-chip ac-coupling capacitors, which avoids the use of large, off-chip capacitors or slow, rail-to-rail input stages. The small coupling capacitance and bias switches generate a pseudo return-to-zero pulse that is latched into the receiver via digital feedback. This input latching reduces the effects of baseline wander caused by unbalanced data streams without the need for encoding or scrambling. In addition, the full-scale digital feedback is used as the receiver output, enabling direct interface with standard digital cells. The architecture is implemented in a 130-nm SiGe BiCMOS and 45-nm CMOS silicon-on-insulator (SOI) technology. The 130-nm SiGe BiCMOS design achieves a peak data rate of 10 Gb/s at 5.1 mW, while a peak efficiency of 0.46 mW/Gb/s is recorded at 8 Gb/s. The 45-nm CMOS SOI design achieves a peak data rate of 30 Gb/s at 12.02 mW, with a peak efficiency of 0.24 mW/Gb/s at 25 Gb/s. Both the SiGe BiCMOS and CMOS SOI designs exhibit BERs of <;10-12 with PRBS15 data as small as 100 mV and occupy 0.012 and 0.007 mm2, respectively, including the on-chip coupling capacitance.
Takarabt, Sofiane; Chibani, Kais; Facon, Adrien; Guilley, Sylvain; Mathieu, Yves; Sauvage, Laurent; Souissi, Youssef
Pre-silicon Embedded System Evaluation as New EDA Tool for Security Verification Proceedings Article
In: 2018 IEEE 3rd International Verification and Security Workshop (IVSW), pp. 74-79, 2018.
@inproceedings{8494881,
title = {Pre-silicon Embedded System Evaluation as New EDA Tool for Security Verification},
author = {Sofiane Takarabt and Kais Chibani and Adrien Facon and Sylvain Guilley and Yves Mathieu and Laurent Sauvage and Youssef Souissi},
doi = {10.1109/IVSW.2018.8494881},
year = {2018},
date = {2018-07-01},
booktitle = {2018 IEEE 3rd International Verification and Security Workshop (IVSW)},
pages = {74-79},
abstract = {The security evaluation of embedded systems becomes clear and mandatory. Up today, the evaluation process is limited to certification labs that conduct the analysis on real target devices. This requires appropriate measurement platforms and equipment in addition to real chip analysis skills. In this paper, we put forward a pre-silicon evaluation methodology and tools that allow the security verification at an early stage (virtual target) and running it hands in hands with the functional verification. As of today, such approach can be used as new Electronic Design Automation (EDA) tool to properly satisfy the basics of Design for Security (DFS) concept. From a practical viewpoint, we show a study case to illustrate and provide a better understanding of that approach. Moreover, we propose new evaluation metrics based on Signal to Noise Ratio (SNR) computation, and verified on virtual and real targets respectively based on a comparative study. Likewise, the tool identifies vulnerabilites (thereby anticipating complete families of otherwise numerous, complex and many undiscovered attacks), and returns accurate feedack to the user on the precise line of code (LoC) where the vulnerability lays along with its characterization, including an identification of its severity. This allows the design to input source code to the tool, and to get back in return annotated source code with a collection of LoCs which deserve careful analysis and/or subsequent modification aiming at patching vulnerabilities.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
The security evaluation of embedded systems becomes clear and mandatory. Up today, the evaluation process is limited to certification labs that conduct the analysis on real target devices. This requires appropriate measurement platforms and equipment in addition to real chip analysis skills. In this paper, we put forward a pre-silicon evaluation methodology and tools that allow the security verification at an early stage (virtual target) and running it hands in hands with the functional verification. As of today, such approach can be used as new Electronic Design Automation (EDA) tool to properly satisfy the basics of Design for Security (DFS) concept. From a practical viewpoint, we show a study case to illustrate and provide a better understanding of that approach. Moreover, we propose new evaluation metrics based on Signal to Noise Ratio (SNR) computation, and verified on virtual and real targets respectively based on a comparative study. Likewise, the tool identifies vulnerabilites (thereby anticipating complete families of otherwise numerous, complex and many undiscovered attacks), and returns accurate feedack to the user on the precise line of code (LoC) where the vulnerability lays along with its characterization, including an identification of its severity. This allows the design to input source code to the tool, and to get back in return annotated source code with a collection of LoCs which deserve careful analysis and/or subsequent modification aiming at patching vulnerabilities.
Khanna, Punit; Rebeiro, Chester; Hazra, Aritra
XFC: A Framework for eXploitable Fault Characterization in Block Ciphers Proceedings Article
In: ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1-6, DAC ACM/IEEE/EDAC, 2017, ISBN: 978-1-4503-4927-7.
@inproceedings{Khanna2017,
title = {XFC: A Framework for eXploitable Fault Characterization in Block Ciphers},
author = {Punit Khanna and Chester Rebeiro and Aritra Hazra},
url = {https://ieeexplore.ieee.org/document/8060292},
doi = {10.1145/3061639.3062340},
isbn = {978-1-4503-4927-7},
year = {2017},
date = {2017-05-08},
booktitle = {ACM/EDAC/IEEE Design Automation Conference (DAC)},
pages = {1-6},
publisher = {ACM/IEEE/EDAC},
organization = {DAC},
abstract = {Fault attacks recover secret keys by exploiting faults injected during the execution of a block cipher. However, not all faults are exploitable and every exploitable fault is associated with an offline complexity to determine the key. The ideal fault attack would recover maximum key bits with minimum offline effort. Finding the ideal fault attack for a block cipher is a laborious manual task, which can take several months to years before such an attack is discovered. In this paper, we present a framework that would analyze block ciphers for their vulnerabilities to faults and automatically predict whether a differential fault attack would be successful. The framework, which we call XFC, uses colors to analyze the fault propagation and exploitability in the cipher. XFC would be able to (a) predict the key bits that can be derived by the fault attack and (b) estimate the offline complexity. It can thus be used to identify the ideal fault attack for a block cipher. As a proof of concept, we have applied XFC to the block ciphers AES, CLEFIA, and SMS4 and were able to automatically derive fault attacks that correspond to the best known to date in the single fault model.},
keywords = {},
pubstate = {published},
tppubtype = {inproceedings}
}
Fault attacks recover secret keys by exploiting faults injected during the execution of a block cipher. However, not all faults are exploitable and every exploitable fault is associated with an offline complexity to determine the key. The ideal fault attack would recover maximum key bits with minimum offline effort. Finding the ideal fault attack for a block cipher is a laborious manual task, which can take several months to years before such an attack is discovered. In this paper, we present a framework that would analyze block ciphers for their vulnerabilities to faults and automatically predict whether a differential fault attack would be successful. The framework, which we call XFC, uses colors to analyze the fault propagation and exploitability in the cipher. XFC would be able to (a) predict the key bits that can be derived by the fault attack and (b) estimate the offline complexity. It can thus be used to identify the ideal fault attack for a block cipher. As a proof of concept, we have applied XFC to the block ciphers AES, CLEFIA, and SMS4 and were able to automatically derive fault attacks that correspond to the best known to date in the single fault model.